Want solution for Shift/reduce conflict in VHDL grammar

Discussion in 'VHDL' started by saorjag1729, Dec 28, 2007.

  1. saorjag1729

    saorjag1729

    Joined:
    Dec 3, 2007
    Messages:
    1
    Hi,
    I have a VHDL grammar in bison(LALR(1) format).
    I am facing a shift/reduce problem as follows.

    range_attribute_name
    : attribute_prefix T_RANGE
    {
    ;
    }
    | attribute_prefix T_REVERSE_RANGE
    {
    ;
    }
    ;

    attribute_name
    : attribute_prefix T_IDENTIFIER
    {
    ;
    }
    | range_attribute_name
    {
    ;
    }
    ;

    range_attribute_name_with_param
    : range_attribute_name
    {
    ;
    }
    | range_attribute_name T_LEFTPAREN expr T_RIGHTPAREN
    {
    ;
    }
    ;
    range_spec
    : range_attribute_name_with_param
    {
    ;
    }
    | expr direction expr
    {
    ;
    }
    ;

    while reducing range_attribute_name it will point to both the non-terminals "attribute_name" and "range_attribute_name_with_param"

    239 attribute_name: range_attribute_name .
    240 range_attribute_name_with_param: range_attribute_name .
    241 | range_attribute_name . T_LEFTPAREN expr T_RIGHTPAREN

    T_LEFTPAREN shift, and go to state 682

    T_GENERATE reduce using rule 240 (range_attribute_name_with_param)
    T_LOOP reduce using rule 240 (range_attribute_name_with_param)
    T_LEFTPAREN [reduce using rule 239 (attribute_name)]
    T_RIGHTPAREN reduce using rule 240 (range_attribute_name_with_param)
    T_COMMA reduce using rule 240 (range_attribute_name_with_param)
    $default reduce using rule 239 (attribute_name)

    I want a solution to fix the above problem.

    It will be great helpful for me.

    Thanks in advance.
    Viru
     
    saorjag1729, Dec 28, 2007
    #1
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