Warning of Xst:2677

Discussion in 'VHDL' started by Sudeep Vhdl-Rookie, Apr 11, 2007.

  1. I am getting a warning of My Array is not connecting to the block.
    when i test bench it i am getting 'U's.


    WARNING:Xst:2677 - Node <COUNT_3_0> of sequential type is unconnected
    in block <MemMod2d>.


    Sample code:
    architecture Behavioral of MemMod2d is
    type MEM1 is array (0 to 255) of STD_LOGIC_VECTOR (7 downto 0); -- 1d
    x 1d
    signal COUNT: MEM1;

    begin

    DataIn: process (pixdata,clk,Reset_Frame)

    begin
    if (Reset_Frame = '1') then

    if (clk'event and clk = '0') then
    For i in 0 to 255 Loop
    if (pixdata = i) then
    COUNT (i) <= COUNT (i)+ "1";

    end loop;
    end if;
    end if;


    end process DataIn;
     
    Sudeep Vhdl-Rookie, Apr 11, 2007
    #1
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  2. Sudeep Vhdl-Rookie

    Andy Peters Guest

    On Apr 11, 11:17 am, "Sudeep Vhdl-Rookie" <> wrote:
    > I am getting a warning of My Array is not connecting to the block.
    > when i test bench it i am getting 'U's.
    >
    > WARNING:Xst:2677 - Node <COUNT_3_0> of sequential type is unconnected
    > in block <MemMod2d>.


    Oy! Where to begin ...

    > Sample code:
    > architecture Behavioral of MemMod2d is
    > type MEM1 is array (0 to 255) of STD_LOGIC_VECTOR (7 downto 0); -- 1d
    > x 1d
    > signal COUNT: MEM1;
    >
    > begin
    > DataIn: process (pixdata,clk,Reset_Frame)
    > begin
    > if (Reset_Frame = '1') then
    > if (clk'event and clk = '0') then
    > For i in 0 to 255 Loop
    > if (pixdata = i) then
    > COUNT (i) <= COUNT (i)+ "1";
    > end loop;
    > end if;
    > end if;
    > end process DataIn;


    Let's see ... first of all, XST is probably as confused by your code
    as I am. pixdata shouldn't be on the sensitivity list if your intent
    is to build synchronous logic (looks like you want an array of
    counters). Also, the falling clock edge shouldn't be inside the
    Reset_Frame "if" block.

    Finally, nothing ever properly initializes COUNT. Think about the
    statement:

    COUNT(i) <= COUNT(i) + "1";

    I don't see anything that loads a value into any of the elements of
    COUNT(i), so of course when you first use it, COUNT(i) has the value
    "UUUUUUUU". Adding 1 to "UUUUUUUU" is still "UUUUUUUUU."

    -a
     
    Andy Peters, Apr 11, 2007
    #2
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  3. On 11 Apr 2007 11:17:33 -0700, "Sudeep Vhdl-Rookie"
    <> wrote:

    >Sample code:


    >architecture Behavioral of MemMod2d is
    > type MEM1 is array (0 to 255) of STD_LOGIC_VECTOR (7 downto 0);
    > signal COUNT: MEM1;
    >begin
    > DataIn: process (pixdata,clk,Reset_Frame)
    > begin
    > if (Reset_Frame = '1') then
    > if (clk'event and clk = '0') then
    > For i in 0 to 255 Loop
    > if (pixdata = i) then
    > COUNT (i) <= COUNT (i)+ "1";
    > end loop;
    > end if;
    > end if;
    > end process DataIn;


    I totally agree with everything Andy Peters said.

    A few other points:

    (1)
    Try using only 2-space indents. It makes the code far
    easier to read.

    (2)
    Is this to gather an image histogram? If so, you should question
    whether 8-bit counters are wide enough. Images often have many
    thousands of pixels of the same colour - especially saturated white
    or black. Your counters will wrap round from 255 to 0, giving
    confusing results. You already have a lot of counters; increasing
    their width to perhaps 12 bits would not be a huge overhead.

    (3)
    I suspect it's wrong for Reset_Frame to be in the sensitivity list.
    Surely you have a *synchronous* frame reset signal?

    (4)
    How are you planning on getting data *out* of the counters?
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
     
    Jonathan Bromley, Apr 12, 2007
    #3
  4. Sudeep Vhdl-Rookie

    vipinlal

    Joined:
    Feb 25, 2010
    Messages:
    38
    hope this helps..
    vhdlguru.blogspot.com/2010/03/synthesis-warning-node-of-sequential.html
     
    vipinlal, Mar 11, 2010
    #4
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