There is no need to reset every flip-flop in a design. A reset signal that
breaks any feedback loops so that the design is in a known state after some
number of clock cycles with the feedback loop and inputs forced is sufficient.
For example, a DSP design typically has a pipelined data path with little or no
feedback, and some sort of sequencer. It is sufficient to reset the sequencer,
and hold the inputs at a known state (typically zero) long enough for any data
in the pipeline to propagate out. If you also hold the outputs at zero while
the reset sequence is in progress, it becomes impossible to tell the difference
from outside the chip between a reset that clears every last flip-flop and one
that holds the input, output and a few key points at reset for some
predetermined length of time. The latter doesn't chew up routing and LUT
resources the way the reset everything approach does.
jakab said:
On the "can of worms"...since it is allready opened:
If you don't have a reset how you bring the FPGA logic into a known
state without power cycle?
--
--Ray Andraka, P.E.
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