Writing state machine output signals.

Discussion in 'VHDL' started by Fred Bartoli, Dec 18, 2004.

  1. Fred Bartoli

    Fred Bartoli Guest

    Hello,

    I now have a complex behavioral model that I'm rewriting in order to make
    the RTL model and I have a complex state machine (1 process SM style).


    Here's an excerpt for one state :

    case CellState is
    when Idle =>
    ..
    ..
    ..

    when Wait_CluTOT =>
    if IsBoundaryCell = '1' then
    IsHighest_TOT := true;
    TOT_Out <= TOT;
    if IsSigCell = '0' then
    CellResolved <= '1';
    end if;
    CellState := Resolve_TOT;
    end if;
    if (ResolveCell = '1') then
    if HighTOT then
    IsHighest_TOT := true;
    StopNextCells <= '1';
    TOT_Out <= TOT;
    else
    TOT_Out <= TOT_In;
    end if;
    if IsSigCell = '0' then
    CellResolved <= '1';
    end if;
    CellState := Resolve_TOT;
    end if;

    ..
    ..
    ..
    when...

    end case;

    Apart from cleaning up the code and make it maybe more readable, I'm
    wondering what is the best writing style for the outputs updating :
    update one output after another and duplicate conditions, and then update
    the state,
    or
    write the conditions and duplicate the states and outputs updates, as it is
    written?

    Does this have an impact on the final result or does the synthesizers do a
    good job of optimizing all this ?
    I ask this mainly because the overall state machine is about 140 LUTs and I
    have 256 of those in my design.

    Any input/comments/thought appreciated.


    --
    Thanks,
    Fred.
     
    Fred Bartoli, Dec 18, 2004
    #1
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  2. Fred Bartoli wrote:

    > Apart from cleaning up the code and make it maybe more readable, I'm
    > wondering what is the best writing style for the outputs updating :
    > update one output after another and duplicate conditions, and then update
    > the state, or
    > write the conditions and duplicate the states and outputs updates, as it is
    > written?


    Looks ok to me, but you only show one case.
    Unless a condition is repeated in every case,
    you can't pull it out, but you might tidy
    up using functions and/or procedures.

    Sometimes it makes sense to set an output
    in one state/condition, clear it in another
    and don't mention it otherwise.

    But don't start cleaning up until you've
    run a sim to see that it is running
    like you expect.

    > Does this have an impact on the final result


    Order only matters with variable values.
    If you get this wrong, you will see it
    in simulation. Otherwise it's style.
    For complicated outputs, I declare
    a process variable, say my_out_v, update
    that through the cases, then do a
    my_out <= my_out_v;
    at the end of the process.

    > or does the synthesizers do a
    > good job of optimizing all this ?
    > I ask this mainly because the overall state machine is about 140 LUTs and I
    > have 256 of those in my design.


    Generally yes, a very good job.
    But don't listen to me, try it and see.

    > Any input/comments/thought appreciated.


    Read this:
    http://www.designabstraction.co.uk/HTML/articles.htm

    -- Mike Treseler
     
    Mike Treseler, Dec 18, 2004
    #2
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