Xilinx 6.2 - - WARNING:NetListWriters:303

Discussion in 'VHDL' started by Rudi Grave, Jun 9, 2004.

  1. Rudi Grave

    Rudi Grave Guest

    Hello, I get following warning in the "Simulate Post Translate VHDL
    Model" :

    WARNING:NetListWriters:303 - Unable to preserve the ordering for port
    bus S on
    block dft8 using the data S<0><7:0>.

    I don't know where it comes from and what to do. On the Xilinx pages I
    can't find any help.

    The first Simulation tools runs without an error.

    The Port Declaration is:

    Port ( C : in std_logic_vector(7 downto 0);
    dataready : in std_logic;
    clk : in std_logic;
    reset: in std_logic;
    S : out Syndrom);
    Syndrom is defined in a package as

    type Syndrom is array (0 to r-1) of std_logic_vector(7 downto 0);

    If you have any idea what the reason for the message please write back
    Rudi
    Rudi Grave, Jun 9, 2004
    #1
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