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VHDL
Creating a delay with VHDL without using wait (n00b)
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[QUOTE="vipinlal, post: 4037225, member: 64505"] 'wait for' statement is useless when it comes to synthesize.you can actually use a mod-n counter for generating a delay. vhdlguru.blogspot.com/2010/03/synthesizable-delay-generator-instead.html [/QUOTE]
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Creating a delay with VHDL without using wait (n00b)
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