Creating a delay with VHDL without using wait (n00b)

P

pat_jakubowski

Let me begin by saying that I am new to VHDL.

I would like to create a delay in my VHDL code because I need to hold
an external clock low for a specified amount of time. I understand
that I have to implement this using clock division and counters since
the wait instruction doesn't synthesize. However, I am unsure of
exactly how to do this.

If I use the board clock, will it run at 50Mhz as specified in the
manual or will it run at the "maximum operating frequency" as specified
in the synthesis report? This is necessary to know in order to know
how much to divide the clock by.

Thank you very much for your help...
 
M

Mark McDougall

If I use the board clock, will it run at 50Mhz as specified in the
manual or will it run at the "maximum operating frequency" as specified
in the synthesis report? This is necessary to know in order to know
how much to divide the clock by.

A 50MHz clock source will run at 50MHz.

The maximum operating frequency is the maximum frequency at which your
design will theoretically run in that piece of silicon.

You need a counter to divide down your clock. For a fully synchronous
design, you will actually be creating a 'clock enable' rather than a
clock signal - there's a difference, and it'll only be active for 1
50MHz period, not 50% duty cycle.

If your counter is too large (i.e. you need to wait a long time) you may
need to pipeline it to speed up your design.

Regards,
 
W

wallge

If you are using an altera device,
just instantiate a phased locked loop mega function
via the mega function wizard in quartus II.
The GUI will guide you through the process
you specify input clock speed,
and the number and frequency of output clocks.
After you're done running through the wizard,
simply instantiate the PLL component in your VHDL
design and connect clock signals to it as appropriate.

If you are using xilinx, the tool for generating useful components
is called core-gen, and has similar functionality to the altera tool.
 
Joined
Feb 25, 2010
Messages
38
Reaction score
0
'wait for' statement is useless when it comes to synthesize.you can actually use a mod-n counter for generating a delay.
vhdlguru.blogspot.com/2010/03/synthesizable-delay-generator-instead.html
 

Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.

Ask a Question

Members online

Forum statistics

Threads
473,744
Messages
2,569,483
Members
44,901
Latest member
Noble71S45

Latest Threads

Top