Generating a 78MHz clock from a 100MHz base clock (VHDL)

Discussion in 'VHDL' started by pierpaolo.bagnasco, Nov 11, 2012.

  1. I have to generate a 78MHz clock (duty cycle 0.5 or 0.7) from a 100MHz baseclock (duty cycle 0.5) using VHDL language (so the ratio is 200/156). I know that I can use DCM, PLL or similar, but at this moment (unfortunately) Ijust can't.

    Therefore I thought to use (excluding any DCM or PLL) a simple frequency divider, but in this case I also know that the frequency can be divided only by integer numbers (and minimum 2, because I would use counters to do that - and In my case I have to divide the base clock by 1,2820512820512820512820512820513...).

    So I have no idea how to realize that without using any DCM or other stuff.... I thought to divide the 100MHz clock in smaller frequencies (like 50MHz,25MHz etc.) and adding them (50+25+3 for example), but is this the right way (logically I don't think so)?

    So, have you some suggests?
    pierpaolo.bagnasco, Nov 11, 2012
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  2. pierpaolo.bagnasco

    Gabor Guest

    Whether you can do anything useful with counters depends on the clock
    requirements. You can certainly use direct digital frequency synthesis
    to generate the required 78 MHz - on average. Unless you use both
    clock edges, the jitter will be 10 ns, which is very large for many
    applications, but might be OK if you're just dividing this down to
    clock a UART for example. Using both edges of 100 MHz you still end
    up with 5 ns of jitter. If that isn't good enough you really need
    to use a PLL or DCM to do the job.

    -- Gabor
    Gabor, Nov 11, 2012
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  3. pierpaolo.bagnasco

    Rob Gaddi Guest

    On Sun, 11 Nov 2012 01:16:57 -0800 (PST)
    You can't do what you're trying to do, or at least not reliably.

    If you were SUPREMELY desperate you could build an NCO to drive a pin
    or two as a poor-man's DAC (you're up above Nyquist, so you'd have to
    be clever here), then use an LC filter to trap 78 MHz, a Schmitt
    trigger to square it back up, then feed it back into the chip.

    I feel like we should write this question over the door here: "What is
    it you're actually trying to accomplish that makes you think you need
    Rob Gaddi, Nov 12, 2012
  4. pierpaolo.bagnasco

    rickman Guest

    I don't agree. You just need to think outside of the box.

    How about of circuit that uses both edges of the 50% duty cycle 100 MHz
    clock? That would give you a virtual 200 MHz clock with a resolution of
    5 ns. This gives a base error of 22% worse case, not including
    propagation deltas in the clock and I/O routing.

    This is not an easy circuit to design, but it can be done I think. This
    will require a double clocked counter with two registers and two adders.
    Think of it as two phased...

    The results of the two adders will be logically combined to produce two
    phases of the output which would be combined in a DDR type output. If
    the DDR output isn't supported, then the two phases would have to be
    xored in a single LUT before being output. This should produce a clock
    with 5 ns resolution and little edge jitter if manually placed

    If this is not clear I can provide some HDL, but that might take a
    little time and I don't have much today.

    rickman, Nov 12, 2012
  5. pierpaolo.bagnasco

    BLue39 Guest

    Hi pierpaolo,

    The method I'm suggesting is dependent on the FPGA you are using.

    In the XILINX FPGA's there's a structure called "Carry Chain", which is a complete combinational circuit. You will have to generate a 100 MHz clock with 155 degree phase shift. (You will have to perform experimentations and find the number of the carry chain numbers you will require; this number actually is device dependent.)
    Similarly you generate clocks with 78 degree and 235 degree phase shift.

    Thus you have 3 clocks in the picture. All having frequencies of 100 MHz, but their phase 0, 78, 155, 235 degrees. Call them clk1, clk2, clk3 and clk4respectively.

    Suppose your final 78 MHz clock is named as clk_78.
    Then you will have to toggle its value according to the below event order.

    1. Toggle when rising_edge of clk1.
    2. Toggle when rising_edge of clk2.
    3. Toggle when rising_edge of clk3.
    4. Toggle when rising_edge of clk4.
    5. Again go to step1.

    To follow this order, you'll have to do a clever clock muxing of clk1, clk2, clk3 and clk4.
    Notice we are not changing clk_78's value at every rising edge of any of the 4 clocks.

    I know this is a very complex way and you'll have to perform manual routingand take care of the routing delays.

    But, I can think of this only way of multiplying/dividing your 100 MHz clock with such an odd figure.

    BLue39, Dec 24, 2012
  6. pierpaolo.bagnasco

    Andy Guest

    Ummm... NO, this won't work.

    Even if you solve the placement and routing, and overlook the temperature/voltage dependencies of the phase delays, the pattern has an additional phase delay getting back to step 1. Toggling the new clock signal four times every 100 MHz will still yield an average frequency of 50 MHz.

    Just supposing it would work (which it won't), there are ways to toggle a signal on multiple clocks without muxing the clocks. Look up "Flancter circuit".

    Andy, Jan 7, 2013
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