change a clock to pulse in vhdl

[JSreeniv]

Hi all,

I am getting difficult in simulating the vhdl code which is having a
pulse train input signal x_in (20 ns period) which is synchronus to
fpga clock of frequency 50 MHz.
In my VHDL code pulse train is applicable for counting number of
pulses in defined time base after that code is changes to find only
high pulse (or counts in given high pulse of defined time base with
change in x_in input signal of low for 50 ns and high for 1000 ns);
the difificult i am facing is how to change pulse train x_in to just
a high pulse or low pulse signal.

Simulation is not happening when i use x_in signal to high or low
pulse signal.
Please give some knowledge on this simulation issue, if anything more
information i can provide.

Thanks,
Sreenu

 

[Mike Treseler]

I am getting difficult in simulating the vhdl code which is having a
pulse train input signal x_in (20 ns period) which is synchronous to
fpga clock of frequency 50 MHz.

I use a synchronous delay to create testbench stimulus.
See below or
http://mysite.verizon.net/miketreseler/test_uart.vhd
for details.

-- Mike Treseler



--------------------------------------------------------------
procedure tic is
begin
wait until rising_edge(clk_s);
end procedure tic;
--------------------------------------------------------------
procedure set_bit (signal arg_s : inout std_ulogic) is
begin-- skip tic if already set
if arg_s /= '1' then
arg_s <= '1';
tic;
end if;
end procedure set_bit;
--------------------------------------------------------------
procedure clr_bit (signal arg_s : inout std_ulogic) is
begin -- skip tic if already clear
if arg_s /= '0' then
arg_s <= '0';
tic;
end if;
end procedure clr_bit;