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VHDL
intialisation of matrix of integers
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[QUOTE="mohansriram, post: 5046023, member: 79443"] please help me how to initialise a matrix containing integers of order 2x2 . . . . . . . . >what is the problem in following program, i could'nt understand: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity test_12 is port(a,b,c,d:in integer;e,f,g,h: out std_logic_vector(4 downto 0)); end test_12; architecture behv of test_12 is type a11 is array(1 to 2,1 to 2) of std_logic_vector(2 downto 0); type b11 is array(1 to 2,1 to 2) of std_logic_vector(2 downto 0); signal sa,sb,sc,sd:signed(3 downto 0); begin sa<= conv_signed(a,4); sb<= conv_signed(b,4); sc<= conv_signed(c,4); sd<= conv_signed(d,4); a11<=((sa,sb),(sc,sd)); process begin e:=a1(1,1)+'1'; end process; end behv; in this program, it was showing that "conv_signed" is unknown identifier but conv_signed is predefined function in std_logic_arith library.... please anyone help me in this program [/QUOTE]
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intialisation of matrix of integers
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