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Can anyone help?
Main tags: opensource, good architectured.
Google, opencores didn't help
Thanks!
Main tags: opensource, good architectured.
Google, opencores didn't help
Thanks!
I have used VPP in the past, I did modify it slightly but I can'tCan anyone help?
Main tags: opensource, good architectured.
Google, opencores didn't help
Thanks!
Can anyone help?
Main tags: opensource, good architectured.
Google, opencores didn't help
Thanks!
I have used VPP in the past, I did modify it slightly but I can't
remember what I changed, anyway you can download the source
http://sourceforge.net/projects/vhdlpp/
Hans
www.ht-lab.com
Hard to find - can you provide some link?
I need it to control matlab->HDL flow easily.Inevitably, they allowed me to write
non-standard code that was more difficult to maintain and work with in
the long run. Yes...
Whatever it is you think you need a preprocessor for, you're probably wrong.
I've used cpp, M4, and my own proprietary code all as VHDL
preprocessors in the past. Inevitably, they allowed me to write
non-standard code that was more difficult to maintain and work with in
the long run.
VHDL is a fantastically extensible language. Whatever it is you think
you need a preprocessor for, you're probably wrong.
Cool link, thanks. Try to collect and optimize all my ideasProbably he isn't as preprocessing is being discussed in the P1076
steering group:
http://www.eda.org/twiki/bin/view.cgi/P1076/VHDLPreprocessor
I do hope we don't end up with the unreadable ' or is it the ` character....
Hanswww.ht-lab.com
Yap. too.I do hope we don't end up with the unreadable ' or is it the ` character....
You mean KPP -- http://klabs.org/richcontent/software_content/kpp.htm
Or i'm wrong?
Hard to find - can you provide some link?
I need it to control matlab->HDL flow easily.
F.E. change vhdl coder output parts for using some FPGA embedded DSP blocks.
etc.
Have my own samples, but do not want to reinvent the wheel in the case ofbone preprocessor![]()
Understood, with all limitationsGood:
super-easy to work with and you already know the syntax. Bad: pretty
limited in terms of what it can do.
Thanks, never heard about it before
Yes, too heavy "add-on" for vhdl. Not an elegant solutionBad: Expect to spend time syntax tuning. Lots and lots of time.
Hmm... might be much prettier.std.textio to read those text files from VHDL to configure things
Preffer matlab/vhdl project makefiles for similar tasks.I've used this technique to create packages that hold
things like Subversion revision, timestamp, etc
My apologies, I write VHDL code since long time; I never need a preprocessor. You coming from software or has formed in some language with cuisine "C" ?
----------------------------------------------------------------Another option would be to have Matlab write out text files, and use
std.textio to read those text files from VHDL to configure things.
That's generally kosher for synthesis so long as your use of textio
only happens at elaboration time. Generally you'd wrap a function
around the textio calls, and have that function return something that
can initialize a constant, that can then make the rest of your code do
what it ought. I've used this technique primarily for initializing
ROMs, filter coefficients, etc.
Or have Matlab write out functions, procedures, or
constants to a VHDL package file, and then use that package in your
main code. I've used this technique to create packages that hold
things like Subversion revision, timestamp, etc, in such a way that
they can be synthesized in.
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