A gray counter

[fofo]

Hello,

I'm trying to write a gray counter 4 bits code and what I'm doing is
counting in binary then arranging in gray ^ ^!
This idea, could it be synthesized and how to think physically when
writing HDL codes? then how to check my code for syntax errors???

Thanks a lot

 

[Gabor]

Hello,

I'm trying to write a gray counter 4 bits code and what I'm doing is
counting in binary then arranging in gray ^ ^!
This idea, could it be synthesized and how to think physically when
writing HDL codes? then how to check my code for syntax errors???

Thanks a lot

The main reason to use a Gray code counter is to make sure only one
output changes at a time for ease of crossing clock-domains. If you
have a standard synchronous binary counter and convert its outputs
into Gray code, you don't really have what you want because there
will be decoding glitches on the Gray coded outputs.

So the first thing you need to realize for synthesis is that you
want to preform the binary to Gray conversion on the "next"
binary count state and then register the Gray converted signals
in the same clock domain as the binary count.

This is pretty common technique for building dual-clocked
FIFO's, so you might want to look for FIFO code for
examples.

-- Gabor

 

[eliascm]

Gray Code Counter

If you go to this site http://www.vhdl.org/comp.lang.vhdl/FAQ1.html and look in FAQ Part 1, Section 4.2.29 "Gray Code Counter Model" you should find what you need.

 

[eliascm]

Another Gray Counter

I like this version of a Gray counter better than the one I suggested in my earlier post.

--Synchronous gray up counter with asynchronous reset
--Adapted from Active-HDL "Lanquage Assistant" Code					  
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use ieee.numeric_std.all;
----------------------------------------------------------------------------------------------------

ENTITY gray_counter IS

GENERIC (width : natural := 16);
PORT (
      reset	       : IN    std_logic;
      ce 	       : IN    std_logic;
     clk    	       : IN    std_logic;
      gray_count : OUT std_logic_vector(width - 1 DOWNTO 0)
     );
END;

ARCHITECTURE struct OF gray_counter IS

BEGIN

  PROCESS (clk, reset)

     variable bin_count          : unsigned(width - 1 DOWNTO 0);
     variable uns_gray_count : unsigned(width - 1 DOWNTO 0);
	
     BEGIN
       IF reset = '1' THEN
         bin_count      := (others => '0');
         uns_gray_count := (others => '0');
         gray_count     <= (others => '0');
       ELSIF rising_edge(clk) THEN
         IF ce = '1' THEN
           bin_count  := bin_count + 1;
           uns_gray_count := ('0' & bin_count(bin_count'length - 1 downto 1)) xor bin_count;
           gray_count <= std_logic_vector(uns_gray_count);
        END IF;
      END IF;
    END PROCESS;

END;