addig delay to modelsim simulation

Discussion in 'VHDL' started by igal001, Oct 21, 2006.

  1. igal001

    igal001

    Joined:
    Oct 21, 2006
    Messages:
    2
    i have a vhdl code with testbanch for modelsim
    i want to see the results of the simulation including delays
    i know that i can do *vho file whis quartus to add delayes to modelsim
    i tryed do this but without any sucsses
    can anyone help me please and describe how to do it
    thanks
     
    igal001, Oct 21, 2006
    #1
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