aggregate operator

[praveen.rajaretnam]

Hi. Can anyone tell me what the aggregate operator in VHDL is???
thanks.

 

[Stephane]

&

 

[Stephane]

& is concatenation; I think it's what you're looking for:

your_signal(31 downto 0) <= bobs_signal(31 downto 24) & "00000000" &
alices_signal(15 downto 8) & that_wire & and_this_one & '1' &
and_so_on(4 downto 0);

 

[praveen.rajaretnam]

thanks for that one... I should have guessed that!