Altera SCFIFO

[ALuPin]

Hi,

I have generated two SCFIFOs with Altera Quartus (4.2 SP1)
MegaWizardManager.

One optimized for best speed (that is Quartus is said to
add output registers)

and one for smallest area (no output registers).

After compiling the two FIFOs I have a look at their
structure in the RTLViewer.

And yet I cannot see any output registers for the "best speed"
optimized one. I can go down the hierachy until I see the
RAM block but there are no additional flipflops between the
RAM block and the outputs of the SCFIFO.

Why ?

Rgds
André

 

[Mike Treseler]

And yet I cannot see any output registers for the "best speed"
optimized one. I can go down the hierachy until I see the
RAM block but there are no additional flipflops between the
RAM block and the outputs of the SCFIFO.

Speed/Area constraints are just hints.
If you know what you want, skip the wizard
and write your own code.

-- Mike Treseler

 

[ALuPin]

Of course one could try to write an own FIFO, it case been
discussed here several times ...

But my question still is why the MegaWizard says

"Output register option for devices with fully synchronous RAM
Would like to register the outputs to maximize performance
but use more area?"
--> YES (best speed)

and YET the RTL viewer does not show an output register stage ?

Rgds
André

 

[Ben Twijnstra]

Hi Andre,

The outp[ut registers are an optional component in the M4K blocks.

To illustrate this, create a dual-port memory using the Plug-in manager. At
a certain point you get to the page where you can select which ports to
register. One of them is the Q output. These output registers are inside
the M4Ks, so you won't see them. If you look at the parameter with which
the SCFIFO instantiates the M4K, you should see a difference.

If not...

Best regards,



Ben

 

[ALuPin]

Hi Ben,

ok, I cannot see it because I cannot look into the M4K block
in the RTL viewer.

Yes the attribute "add_ram_output_register" is differemt, you are
right.


scfifo_component : scfifo
GENERIC MAP (
lpm_width => 9,
lpm_numwords => 32,
lpm_widthu => 5,
intended_device_family => "Cyclone",
lpm_type => "scfifo",
lpm_showahead => "OFF",
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON",
add_ram_output_register => "ON"
)
PORT MAP (
rdreq => rdreq,
aclr => aclr,
clock => clock,
wrreq => wrreq,
data => data,
q => sub_wire0
);