Altera to Xilinx

Discussion in 'VHDL' started by Ronny Hengst, Jul 24, 2003.

  1. Ronny Hengst

    Ronny Hengst Guest

    Hi everybody

    I have my code synthezied to an Altera FPGA and I want to change to a Xilinx
    FPGA. What Problems or Task have to be managed?

    Can anybody help me?

    Thanks
    Ronny Hengst, Jul 24, 2003
    #1
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  2. > > Hi everybody
    > >
    > > I have my code synthezied to an Altera FPGA and I want to change to a

    Xilinx
    > > FPGA. What Problems or Task have to be managed?

    >
    > The pinout will be different for one thing.
    >
    > If your code infers registers, counters, ram etc.,
    > all you have to do is a synth compile for the new device.
    >
    > If your code instances registers, counters, ram etc. from
    > an Altera code generator, it's a redo.
    >


    One difference I found was that the Altera block-RAM implementation allowed
    async reads while the Xilinx version supported sync reads only. This can
    cause truble depending on your desing. If you infer a sync write-async read
    RAM in Xilinx it will be implemented in distributed RAM instead of
    block-RAMs. I also seem to recall that the Altera FIFO implementation had a
    data-counter while the Xilinx version supported only the empty/full flags.
    Xilinx FIFOs can't hold the output data indefinitely (due to the sync RAM
    read behind the scenes) so you might have to add another layer of
    registers/latches, again, depeding on your desing.

    Regards,
    Andras Tantos
    Andras Tantos, Jul 24, 2003
    #2
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