Another Verilog to VHDL converter request

Discussion in 'VHDL' started by Nicolas Matringe, Feb 5, 2007.

  1. Hi all
    I already googled and looked at the FAQ but all I've been able to find
    were dead links.

    I have a processor bus functional model written in Verilog but all my
    design is in VHDL and I don't have a mixed simulation license. Does
    anyone know of a free tool that would help me translate the model in
    VHDL ?

    Thanks in advance
    Nicolas
    Nicolas Matringe, Feb 5, 2007
    #1
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  2. On Feb 5, 2:03 pm, "Nicolas Matringe" <> wrote:
    > Hi all
    > I already googled and looked at the FAQ but all I've been able to find
    > were dead links.
    >
    > I have a processor bus functional model written in Verilog but all my
    > design is in VHDL and I don't have a mixed simulation license. Does
    > anyone know of a free tool that would help me translate the model in
    > VHDL ?
    >
    > Thanks in advance
    > Nicolas


    Nicolas,
    In addition to my separate email on this, I once downloaded a
    tool from:

    http://www02.so-net.ne.jp/~morioka/v2v.htm

    (Now defunct), didn't try it too much, so if you wish either I can
    send you the code/tool or you can send me your code and I can see if I
    can help

    HTH
    Ajeetha, CVC
    www.noveldv.com
    Ajeetha (www.noveldv.com), Feb 5, 2007
    #2
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  3. Ajeetha (www.noveldv.com) a écrit :
    > On Feb 5, 2:03 pm, "Nicolas Matringe" <> wrote:
    >> Hi all
    >> I already googled and looked at the FAQ but all I've been able to find
    >> were dead links.
    >>
    >> I have a processor bus functional model written in Verilog but all my
    >> design is in VHDL and I don't have a mixed simulation license. Does
    >> anyone know of a free tool that would help me translate the model in
    >> VHDL ?
    >>
    >> Thanks in advance
    >> Nicolas

    >
    > Nicolas,
    > In addition to my separate email on this, I once downloaded a
    > tool from:
    >
    > http://www02.so-net.ne.jp/~morioka/v2v.htm
    >
    > (Now defunct), didn't try it too much, so if you wish either I can
    > send you the code/tool or you can send me your code and I can see if I
    > can help


    As I told you in my reply to your e-mail, the BFM is licensed code so I
    can not send it to anyone.
    As someone else suggested (by e-mail again), I can try your URL in a web
    archive service and see if it gives me the code.

    Thanks anyway
    Nicolas
    Nicolas Matringe, Feb 5, 2007
    #3
  4. Nicolas Matringe

    bm Guest

    You could also
    - create an ISE project with the top level module in VHDL instantiating the
    Verilog modules
    - synthetise the design with annotated VHDL generation

    Please provide feedback on the conversion tool if you find it...



    "Nicolas Matringe" <> wrote in message
    news:45c7920b$0$4346$...
    > Ajeetha (www.noveldv.com) a écrit :
    >> On Feb 5, 2:03 pm, "Nicolas Matringe" <> wrote:
    >>> Hi all
    >>> I already googled and looked at the FAQ but all I've been able to find
    >>> were dead links.
    >>>
    >>> I have a processor bus functional model written in Verilog but all my
    >>> design is in VHDL and I don't have a mixed simulation license. Does
    >>> anyone know of a free tool that would help me translate the model in
    >>> VHDL ?
    >>>
    >>> Thanks in advance
    >>> Nicolas

    >>
    >> Nicolas,
    >> In addition to my separate email on this, I once downloaded a
    >> tool from:
    >>
    >> http://www02.so-net.ne.jp/~morioka/v2v.htm
    >>
    >> (Now defunct), didn't try it too much, so if you wish either I can
    >> send you the code/tool or you can send me your code and I can see if I
    >> can help

    >
    > As I told you in my reply to your e-mail, the BFM is licensed code so I
    > can not send it to anyone.
    > As someone else suggested (by e-mail again), I can try your URL in a web
    > archive service and see if it gives me the code.
    >
    > Thanks anyway
    > Nicolas
    bm, Feb 6, 2007
    #4
  5. bm a écrit :
    > You could also
    > - create an ISE project with the top level module in VHDL instantiating the
    > Verilog modules
    > - synthetise the design with annotated VHDL generation


    A bus functionnal model is a processor simulation model. I somehow
    suspect that it is not synthesizable.
    Besides, I need to simulate it (with ModelSim)


    > Please provide feedback on the conversion tool if you find it...


    I tried the one Ajeetah suggested(*) but it choked on every file's first
    line.

    Nicolas

    (*)http://www02.so-net.ne.jp/~morioka/v2v.htm but it actually changed
    address
    Nicolas Matringe, Feb 6, 2007
    #5
  6. On 5 Feb 2007 01:03:20 -0800, "Nicolas Matringe"
    <> wrote:

    >I have a processor bus functional model written in Verilog but all my
    >design is in VHDL and I don't have a mixed simulation license. Does
    >anyone know of a free tool that would help me translate the model in
    >VHDL ?


    I think it is likely to be very difficult.

    Verilog BFMs are generally written in a way that simply does not work
    in VHDL - using cross-module references to call BFM tasks. Over the
    years I have established a methodology for doing the translation by
    hand, and I can usually get reasonable results - but it is not a
    mechanical process, because there are so many different styles for
    writing Verilog BFMs.

    By contrast, translating synthesisable code is usually
    almost trivial (from Verilog to VHDL; if you're going from VHDL
    to Verilog you may have problems with record data types and
    array and type attributes).

    I suggest that the mixed-language simulation licence is probably
    your most viable route. No, I don't work for Mentor sales :)
    --
    Jonathan Bromley, Consultant

    DOULOS - Developing Design Know-how
    VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

    Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK

    http://www.MYCOMPANY.com

    The contents of this message may contain personal views which
    are not the views of Doulos Ltd., unless specifically stated.
    Jonathan Bromley, Feb 6, 2007
    #6
  7. Jonathan Bromley a écrit :

    > I think it is likely to be very difficult.
    >
    > Verilog BFMs are generally written in a way that simply does not work
    > in VHDL - using cross-module references to call BFM tasks. Over the
    > years I have established a methodology for doing the translation by
    > hand, and I can usually get reasonable results - but it is not a
    > mechanical process, because there are so many different styles for
    > writing Verilog BFMs.


    I think I can see your point. I don't have much experience (not at all,
    actually) with Verilog simulation, only RTL.


    > I suggest that the mixed-language simulation licence is probably
    > your most viable route. No, I don't work for Mentor sales :)


    I already contacted my local distributor and got a price. The decision
    is not mine anymore.

    Nicolas
    Nicolas Matringe, Feb 6, 2007
    #7
  8. Nicolas Matringe

    HT-Lab Guest

    "Nicolas Matringe" <> wrote in message
    news:45c8f4ea$0$2270$...
    > Jonathan Bromley a écrit :
    >
    >> I think it is likely to be very difficult.
    >>
    >> Verilog BFMs are generally written in a way that simply does not work
    >> in VHDL - using cross-module references to call BFM tasks. Over the
    >> years I have established a methodology for doing the translation by
    >> hand, and I can usually get reasonable results - but it is not a
    >> mechanical process, because there are so many different styles for
    >> writing Verilog BFMs.

    >
    > I think I can see your point. I don't have much experience (not at all,
    > actually) with Verilog simulation, only RTL.
    >
    >
    >> I suggest that the mixed-language simulation licence is probably
    >> your most viable route. No, I don't work for Mentor sales :)

    >
    > I already contacted my local distributor and got a price. The decision is
    > not mine anymore.


    If you need a mixed license to do your work then I would suggest you speak
    to your manager again. If this is a student project then you might want to
    try the new Modelsim Student license route, see:
    http://www.model.com/resources/student_edition/student_download.asp

    Alternatively, request an evaluation license and work like hell for 30 days
    :)

    Hans
    www.ht-lab.com


    >
    > Nicolas
    HT-Lab, Feb 6, 2007
    #8

  9. > I think I can see your point. I don't have much experience (not at all,
    > actually) with Verilog simulation, only RTL.
    >


    Well I'm told by someone who has worked in Europe that many
    engineers over there (data is some 5 years old) believe that Verilog
    is only for gate Level. If I read your post correctly, that still
    seems to be the case :)

    Why do you say "no verilog, only RTL" - RTL can be in Verilog or
    VHDL.

    Or maybe it was just a typo!

    Ajeetha, CVC
    www.noveldv.com
    Ajeetha (www.noveldv.com), Feb 7, 2007
    #9
  10. Ajeetha posted on 6 Feb 2007 19:49:39 -0800:

    "> I think I can see your point. I don't have much experience (not at all,
    > actually) with Verilog simulation, only RTL.
    >


    Well I'm told by someone who has worked in Europe that many
    engineers over there (data is some 5 years old) believe that Verilog
    is only for gate Level. If I read your post correctly, that still
    seems to be the case :)"

    At where I am based in Europe, VHDL is used as a source language and
    automatically generated Verilog happens to be used by the tool suite
    for the netlists' simulations. We do not produce any handwritten
    Verilog.

    "Why do you say "no verilog, only RTL" - RTL can be in Verilog or
    VHDL.

    Or maybe it was just a typo!"

    Perhaps he was indicating that the only Verilog experience he has is
    with lower level Verilog netlist simulations generated from higher
    level VHDL code instead of high level Verilog simulations.
    Colin Paul Gloster, Feb 7, 2007
    #10
  11. HT-Lab a écrit :

    > If you need a mixed license to do your work then I would suggest you speak
    > to your manager again. If this is a student project then you might want to
    > try the new Modelsim Student license route, see:
    > http://www.model.com/resources/student_edition/student_download.asp


    I wish I still was a student ;)


    > Alternatively, request an evaluation license and work like hell for 30 days
    > :)


    We need 2 licenses AND plan to work like hell for 30 days (as if we
    hadn't already been working like hell for 6 months)

    Nicolas
    Nicolas Matringe, Feb 7, 2007
    #11
  12. Ajeetha (www.noveldv.com) a écrit :
    > Why do you say "no verilog, only RTL" - RTL can be in Verilog or
    > VHDL.
    >
    > Or maybe it was just a typo!


    Not a typo, maybe a bad way of expressing myself.
    I meant "Verilog simulation code" and "Verilog RTL code"

    Nicolas
    Nicolas Matringe, Feb 7, 2007
    #12
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