assigment of signals

Discussion in 'VHDL' started by ZOLVEZ, Oct 4, 2007.

  1. ZOLVEZ

    ZOLVEZ

    Joined:
    Oct 2, 2007
    Messages:
    8
    Hi friends

    I want to do the next:


    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_SIGNED.ALL;

    entity multiplicador is

    Port ( a : in STD_LOGIC_VECTOR (15 downto 0);
    b : in STD_LOGIC_VECTOR (15 downto 0);
    clk : in STD_LOGIC;
    sal : out STD_LOGIC_VECTOR (15 downto 0));

    end multiplicador;

    architecture Behavioral of multiplicador is
    signal tmp : std_logic_vector (31 downto 0);

    begin

    process (clk, a, b)

    begin
    if clk= '1' and clk'event then
    tmp <= a*b;
    end if;

    end process;

    sal<= tmp(23 downto 8 ) ; -- here is the problem

    end Behavioral;




    How you see I want to assign only a portion of de vector 'tmp' to the vector 'sal' I tried to do this using Xilinx ISE 8.1i but it doesn't sinthesize it, so I want to know another way to sinthesize the simple code above. Thanks
     
    ZOLVEZ, Oct 4, 2007
    #1
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