signal assigment

Discussion in 'VHDL' started by ZOLVEZ, Oct 11, 2007.

  1. ZOLVEZ

    ZOLVEZ

    Joined:
    Oct 2, 2007
    Messages:
    8
    Hi


    I want to do the next:


    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_SIGNED.ALL;

    entity multiplicador is
    Port ( a : in STD_LOGIC_VECTOR (15 downto 0);
    b : in STD_LOGIC_VECTOR (15 downto 0);
    clk : in STD_LOGIC;
    sal : out STD_LOGIC_VECTOR (15 downto 0));
    end multiplicador;

    architecture Behavioral of multiplicador is
    signal tmp : std_logic_vector (31 downto 0);
    begin

    process (clk, a, b)
    begin
    if clk= '1' and clk'event then
    tmp <= a*b;
    end if;
    end process;

    sal<= tmp(23 downto 8 ) ; -- Here is the problem
    end Behavioral;



    How you see It’s a simple multiplier, but I want to truncate some bits of the vector ‘tmp’ to assign to the vector ‘sal’. I tried to do this in Xilinx ISE 8.1i software, but it doesn't sinthesize it. Just the following message appear:


    WARNING:Xst:646 - Signal <tmp<31:24>> is assigned but never used.
    WARNING:Xst:646 - Signal <tmp<7:0>> is assigned but never used.



    I would like to know some way to realize and sinthesize the code above. Any suggestions to ZOLVEZ@hotm.... Thanks a lot before hand
     
    Last edited: Oct 11, 2007
    ZOLVEZ, Oct 11, 2007
    #1
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