beginner: 3:8 decoder with enable

Discussion in 'VHDL' started by HaYZaM, Nov 19, 2007.

  1. HaYZaM

    HaYZaM

    Joined:
    Nov 5, 2007
    Messages:
    5
    i want to write the architecture of 3:8 decoder with enable ...

    anyone can help ,

    i wrote the entity
    Code:
    ENTITY Decoder3_8_Enable IS
      port (a: in std_logic_vector(2 downto 0);
            e: in std_logic ;
            y:out std_logic_vector(7 downto 0));
    END ENTITY Decoder3_8_Enable;
     
    HaYZaM, Nov 19, 2007
    #1
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