3:8 decoder with enable

Discussion in 'VHDL' started by HaYZaM, Nov 19, 2007.

  1. HaYZaM

    HaYZaM

    Joined:
    Nov 5, 2007
    Messages:
    5
    Code:
    ENTITY Decoder3_8_Enable IS
      port (a: in std_logic_vector(2 downto 0);
            e: in std_logic ;
            y:out std_logic_vector(7 downto 0));
    END ENTITY Decoder3_8_Enable;
    
    --
    ARCHITECTURE RTL OF Decoder3_8 IS
    BEGIN
      process (e , a)
        begin
          if e = '1' then
             if a="000" then y="00000001"
          elsif a="001" then y="00000010"
          elsif a="010" then y="00000100"
          elsif a="011" then y="00001000"
          elsif a="100" then y="00010000"
          elsif a="101" then y="00100000"
          elsif a="110" then y="01000000"
          elsif a="111" then y="10000000"
          else'--------';
          end if;
       end process  
    END ARCHITECTURE RTL;

    the code doesnt work , anyone know why ?!!
    HaYZaM, Nov 19, 2007
    #1
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  2. HaYZaM

    manasiw2

    Joined:
    Oct 23, 2007
    Messages:
    5
    Hi
    check this modified code...its syntactically correct...please check functionality.



    library ieee;
    use ieee.std_logic_1164.all;

    ENTITY Decoder3_8_Enable IS
    port (a: in std_logic_vector(2 downto 0);
    e: in std_logic ;
    y: out std_logic_vector(7 downto 0)
    );
    END Decoder3_8_Enable;

    --
    ARCHITECTURE RTL OF Decoder3_8_Enable IS
    BEGIN
    process (e , a)
    begin
    if e = '1' then
    if a = "000" then y <="00000001";
    elsif a = "001" then y <="00000010";
    elsif a = "010" then y <="00000100";
    elsif a = "011" then y <="00001000";
    elsif a = "100" then y <="00010000";
    elsif a = "101" then y <="00100000";
    elsif a = "110" then y <="01000000";
    elsif a = "111" then y <="10000000";
    else null;
    end if;
    end if;
    end process;
    END ARCHITECTURE RTL;
    manasiw2, Nov 20, 2007
    #2
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  3. HaYZaM

    forums4f

    Joined:
    Nov 8, 2007
    Messages:
    2
    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std_all
    entity dec is
    port(
    a:in std_ulogic_vector(2 downto 0);
    z : out std_ulogic_vector(7 downto 0);
    e : in std_ulogic); --enable
    end entity ;
    architecture shiftdec of dec is
    constant z_out:bit_vector(7 downto 0):=(0=>'1',others=>'0'); --"00000001";
    begin
    z<=to_stdulogicvector(z_out sll to_integer(unsigned(a))) when e='1' else 'Z';
    end architecture;
    -----------------------
    also
    u can use conv_std_logic_vector (parameter,bit_number)
    conv_integer(parameter)

    use ieee.std_logic_1164.all
    or
    use ieee.std_logic_signed.all
    forums4f, Nov 22, 2007
    #3
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