Dear all,
I do not have much experience with VHDL and synthesis, but I am starting to get some.
I am using Precision RTL synthesis and I am trying to synthesize a design of a state machine. The problem I face is that I have a case statement in each state of the machine and the software detects the "sub" case statement as another state machine, why is that? What can I do to avoid it? I am using an inner case statement to make things easier instead of evaluating conditions several times. In other words, I evaluate the conditions in the initial state, then assign a certain value to a signal and then check this signal in the coming states of the machine.
I do not know if this is a good "VHDL" coding practice but I am just migrating from the programming world and I am having a bad time with VHDL.
Thank you very much.
I do not have much experience with VHDL and synthesis, but I am starting to get some.
I am using Precision RTL synthesis and I am trying to synthesize a design of a state machine. The problem I face is that I have a case statement in each state of the machine and the software detects the "sub" case statement as another state machine, why is that? What can I do to avoid it? I am using an inner case statement to make things easier instead of evaluating conditions several times. In other words, I evaluate the conditions in the initial state, then assign a certain value to a signal and then check this signal in the coming states of the machine.
I do not know if this is a good "VHDL" coding practice but I am just migrating from the programming world and I am having a bad time with VHDL.
Thank you very much.