J
JSreeniv
Hi all,
I am getting difficult in simulating the vhdl code which is having a
pulse train input signal x_in (20 ns period) which is synchronus to
fpga clock of frequency 50 MHz.
In my VHDL code pulse train is applicable for counting number of
pulses in defined time base after that code is changes to find only
high pulse (or counts in given high pulse of defined time base with
change in x_in input signal of low for 50 ns and high for 1000 ns);
the difificult i am facing is how to change pulse train x_in to just
a high pulse or low pulse signal.
Simulation is not happening when i use x_in signal to high or low
pulse signal.
Please give some knowledge on this simulation issue, if anything more
information i can provide.
Thanks,
Sreenu
I am getting difficult in simulating the vhdl code which is having a
pulse train input signal x_in (20 ns period) which is synchronus to
fpga clock of frequency 50 MHz.
In my VHDL code pulse train is applicable for counting number of
pulses in defined time base after that code is changes to find only
high pulse (or counts in given high pulse of defined time base with
change in x_in input signal of low for 50 ns and high for 1000 ns);
the difificult i am facing is how to change pulse train x_in to just
a high pulse or low pulse signal.
Simulation is not happening when i use x_in signal to high or low
pulse signal.
Please give some knowledge on this simulation issue, if anything more
information i can provide.
Thanks,
Sreenu