vhdl testbench sequential

Discussion in 'VHDL' started by JSreeniv, Nov 15, 2009.

  1. JSreeniv

    JSreeniv Guest

    Hi all,
    I doing functional verification for a module called counter in vhdl by
    writing a testbench.

    I have a problem in appying a pulse train with 50% duty cycle in
    between read and write process of my testplan steps.
    In global i hve two clocks:fpga_clk1, dsp_clk1 where in my testbench
    both are generated in the process for this module.
    Here is my test plan.
    1. set power on reset to 0 for 100 ns and then asert to 1;
    2. set two bits1:0 to 11 for software period and set 3:2 to 00 for
    time base 100 ns;(these actions will be done by processor write, ex:
    write(<address of reg>, <value to set>, signal1,signal2....)
    3. HERE IS I WANT TO APPLY PULSE TRAIN with period 50 ns (minimum is
    20 ns) its variable pule train
    4. Laod the count value into the register,its a write process again..
    5.Start measurement

    Here my problem is when i apply pulse train with some period, the next
    write action will be always in ideal no decrement count is happening
    on data bus,....
    If i apply the same pulse train signal in the two clocks place i am
    getting the results.

    But i need to test this system with different pulse train signal
    periods...
    So is there any way to perform this process.

    Even i tried giving a pulse train without "process" in between the
    sequential statements but same problem,..what i understood is the
    pulse train should be synchronus with fpga_clk1, if that is the case
    then how can i perform different pulse train signals.

    Please help me on this..if any other details that i hve to provide
    then please aske me regarding tho this.
     
    JSreeniv, Nov 15, 2009
    #1
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  2. JSreeniv

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Location:
    Denmark
    Could you post your TestBench - or essential parts of it.
     
    jeppe, Nov 15, 2009
    #2
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  3. JSreeniv wrote:

    > But i need to test this system with different pulse train signal
    > periods...
    > So is there any way to perform this process.


    I'm sure there is, but I can't follow your description.
    Maybe you are missing a handshake.
    I do something like this:

    procedure handshake_cycle is
    begin -- example of handshaking loopback data
    wait_for_tx;
    write_data;
    wait_for_rx;
    read_data;
    end procedure handshake_cycle;

    details here: http://mysite.verizon.net/miketreseler/test_uart.vhd

    > Please help me on this..if any other details that i have to provide


    Post a code example that demonstrates the problem.

    -- Mike Treseler
     
    Mike Treseler, Nov 15, 2009
    #3
  4. On 15 Nov., 16:07, JSreeniv <> wrote:

    > Here is my test plan.
    > 1. set power on reset to 0 for 100 ns and then asert to 1;
    > 2. set two bits1:0 to 11 for software period and set 3:2 to 00 for
    > time base 100 ns;(these actions will be done by processor write, ex:
    > write(<address of reg>, <value to set>, signal1,signal2....)
    > 3. HERE IS I WANT TO APPLY PULSE TRAIN with period 50 ns (minimum is
    > 20 ns) its variable pule train
    > 4. Laod the count value into the register,its a write process again..
    > 5.Start measurement


    I see no problem with this testplan. You should describe your
    particular problem in detail.
     
    Thomas Stanka, Nov 16, 2009
    #4
  5. JSreeniv

    JimLewis Guest

    On Nov 15, 7:07 am, JSreeniv <> wrote:
    > Hi all,
    > I doing functional verification for a module called counter in vhdl by
    > writing a testbench.
    >
    > I have a problem in appying a pulse train with 50% duty cycle in
    > between read and write process of my testplan steps.
    > In global i hve two clocks:fpga_clk1, dsp_clk1 where in my testbench
    > both are generated in the process for this module.
    > Here is my test plan.
    > 1. set power on reset to 0 for 100 ns and then asert to 1;
    > 2. set two bits1:0 to 11 for software period and set 3:2 to 00 for
    > time base 100 ns;(these actions will be done by processor write, ex:
    > write(<address of reg>, <value to set>, signal1,signal2....)
    > 3. HERE IS I WANT TO APPLY PULSE TRAIN with period 50 ns (minimum is
    > 20 ns) its variable pule train
    > 4. Laod the count value into the register,its a write process again..
    > 5.Start measurement
    >
    > Here my problem is when i apply pulse train with some period, the next
    > write action will be always in ideal no decrement count is happening
    > on data bus,....
    > If i apply the same pulse train signal in the two clocks place i am
    > getting the results.
    >
    > But i need to test this system with different pulse train signal
    > periods...
    > So is there any way to perform this process.
    >
    > Even i tried giving a pulse train without "process" in between the
    > sequential statements but same problem,..what i understood is the
    > pulse train should be synchronus with fpga_clk1, if that is the case
    > then how can i perform different pulse train signals.
    >
    > Please help me on this..if any other details that i hve to provide
    > then please aske me regarding tho this.


    For every independent action in a testbench, you need a separate
    process.
    So put your pulse train generation logic in a separate process. Then
    provide an enable (a signal at a particular value) to enable it to run
    or not. There are many variations on this pattern, but here is one:

    PulseTrainProc: process
    begin
    if pulse_train_en /= '1' then
    wait until pulse_train_en = '1' ;
    end if ;
    pulse <= '1' ;
    wait for tperiod_pulse_train / 2 ;
    pulse <= '0' ;
    wait for tperiod_pulse_train - tperiod_pulse_train / 2 ; -- integer
    division
    end process ;

    Now in your main testbench process turn the enable on or off as
    needed.

    Cheers,
    Jim
    SynthWorks VHDL Training
     
    JimLewis, Nov 17, 2009
    #5
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