Clarification Term: "Behavioural Description"

Discussion in 'VHDL' started by Nikos Mitas, Sep 26, 2005.

  1. Nikos Mitas

    Nikos Mitas Guest

    In several books for VHDL I have come across the term "behavioural
    description" of a system (circuit etc etc).Is there any other
    description that VHDL can express?Is so what are the differences?
    Nikos Mitas, Sep 26, 2005
    #1
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  2. Nikos Mitas

    james Guest

    On Tue, 27 Sep 2005 00:46:26 +0200, Nikos Mitas <>
    wrote:

    >+<In several books for VHDL I have come across the term "behavioural
    >+<description" of a system (circuit etc etc).Is there any other
    >+<description that VHDL can express?Is so what are the differences?

    *****

    To me, Behavioral Description is using programming language to
    describe a black box operation of a circuit. You need not describe the
    actual contents of what makes up the black box but only to describe
    the input and the output functionality and timing.

    One can also use programing language to describe the structure of a
    block to the gate level and how to hook up the various gates of a
    circuit. Using this method you in a sense use programming language to
    dictate the bounds of the synthesizer. In a behavioral description you
    use constraint files built into the tools to guide and give
    intelligence to help the synthesizer develope a circuit and wiring.


    An example is a full adder. You can describe the behavior as:

    A <= B + C.

    Or you can describe the XOR and AND gates plus how they are wired.
    Both do functionaly the same.

    james
    james, Sep 27, 2005
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  3. Nikos Mitas

    Hubble Guest

    In behavioural, you can (sometimes) omit clocks etc.

    There are other descriptions:

    structural - a (description of a) digital circuit connecting
    components using (signal) wires
    gate-level - structural, but using logic elements from a vendor
    library as components
    register-transfer-level: using processes mostly with clk/reset can
    be synthesized, glitch-resistent
    ...

    a gate-level VHDL description can be the result of a synthesis tool,
    which is fed by a register-transfer-level description.

    A behavioural description (aka behaviour model) can normally not be
    synthesized to a gate-level "netlist".

    In VHDL, at the lowest level (inside the components), there are always
    processes (all concurrent statements can be replaced to equivalent to
    process descriptions, the language reference manual describes how to do
    this).

    Hubble.
    Hubble, Sep 27, 2005
    #3
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