clk synchronization of reset signal

Discussion in 'VHDL' started by axr0284, Feb 6, 2009.

  1. axr0284

    axr0284 Guest

    Hi,
    I am using a Xilinx Spartan 3E for this design
    I have a clk and a reset coming from an external source to the fpga. I
    cannot be sure of the setup and hold time of the reset signal with
    respect to the clk.
    I usually use the double buffer method to synchronize any external
    signal to the clk.

    I would like to use the reset to reset my internal logic (Everything
    is synchronously reset) but I am wondering if the external reset
    signal need to go through the double buffer too before being sent to
    the logic.
    If yes, then what do I use to reset my double buffer?

    Thanks for the help
    Amish
     
    axr0284, Feb 6, 2009
    #1
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  2. axr0284

    jeppe

    Joined:
    Mar 10, 2008
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    Denmark
    Hi

    I would say no, but then agian - it will properly do no harm to synchronize the Reset signal as well.
     
    jeppe, Feb 7, 2009
    #2
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  3. axr0284

    Aiken Guest

    For student level design: Don't need to use any buffer..(just directly
    connect the reset to the internal reset)
    For product level design: Add two buffer to work as Async set the rest
    and Sync release the reset.

    so your internal release reset edge will not have chance happen at the
    rising edge of the clock

    On Feb 6, 6:23 pm, axr0284 <> wrote:
    > Hi,
    > I am using a Xilinx Spartan 3E for this design
    > I have a clk and a reset coming from an external source to the fpga. I
    > cannot be sure of the setup and hold time of the reset signal with
    > respect to the clk.
    > I usually use the double buffer method to synchronize any external
    > signal to the clk.
    >
    > I would like to use the reset to reset my internal logic (Everything
    > is synchronously reset) but I am wondering if the external reset
    > signal need to go through the double buffer too before being sent to
    > the logic.
    > If yes, then what do I use to reset my double buffer?
    >
    > Thanks for the help
    > Amish
     
    Aiken, Feb 9, 2009
    #3
  4. axr0284

    Guest

    On 9 פברו×ר, 18:00, Aiken <> wrote:
    > For student level design: Don't need to use any buffer..(just directly
    > connect the reset to the internal reset)
    > For product level design: Add two buffer to work as Async set the rest
    > and Sync release the reset.
    >
    > so your internal release reset edge will not have chance happen at the
    > rising edge of the clock
    >
    > On Feb 6, 6:23 pm, axr0284 <> wrote:
    >
    > > Hi,
    > > I am using a Xilinx Spartan 3E for this design
    > > I have a clk and a reset coming from an external source to the fpga. I
    > > cannot be sure of the setup and hold time of the reset signal with
    > > respect to the clk.
    > > I usually use the double buffer method to synchronize any external
    > > signal to the clk.

    >
    > > I would like to use the reset to reset my internal logic (Everything
    > > is synchronously reset) but I am wondering if the external reset
    > > signal need to go through the double buffer too before being sent to
    > > the logic.
    > > If yes, then what do I use to reset my double buffer?

    >
    > > Thanks for the help
    > > Amish




    To synchronize or not to synchronize an asynchronous global reset
    input
    http://bknpk.no-ip.biz/HWtips/asynchronousReset.html
     
    , Feb 10, 2009
    #4
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