clk synchronization of reset signal

[axr0284]

Hi,
I am using a Xilinx Spartan 3E for this design
I have a clk and a reset coming from an external source to the fpga. I
cannot be sure of the setup and hold time of the reset signal with
respect to the clk.
I usually use the double buffer method to synchronize any external
signal to the clk.

I would like to use the reset to reset my internal logic (Everything
is synchronously reset) but I am wondering if the external reset
signal need to go through the double buffer too before being sent to
the logic.
If yes, then what do I use to reset my double buffer?

Thanks for the help
Amish

 

[jeppe]

Hi

I would say no, but then agian - it will properly do no harm to synchronize the Reset signal as well.

 

[Aiken]

For student level design: Don't need to use any buffer..(just directly
connect the reset to the internal reset)
For product level design: Add two buffer to work as Async set the rest
and Sync release the reset.

so your internal release reset edge will not have chance happen at the
rising edge of the clock

 

[beky4kr]

For student level design: Don't need to use any buffer..(just directly
connect the reset to the internal reset)
For product level design: Add two buffer to work as Async set the rest
and Sync release the reset.

so your internal release reset edge will not have chance happen at the
rising edge of the clock

To synchronize or not to synchronize an asynchronous global reset
input
http://bknpk.no-ip.biz/HWtips/asynchronousReset.html