Clock Process?

Discussion in 'VHDL' started by Moikel, Mar 8, 2006.

  1. Moikel

    Moikel Guest

    Hey all,

    I'm doing a project for college were I'm building a simple register
    file. However, one part of the assignment has me confused. I need to
    design a clock process which is high for 5ns and low for 25ns. I'm
    using VHDL (of course).

    Could somebody please help me with this?

    Thanks a lot,

    Moikel
    Moikel, Mar 8, 2006
    #1
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  2. Moikel

    Guest

    You are talking about a Clock Process .
    So what clock frequency are you using ?

    Rgds
    André
    , Mar 8, 2006
    #2
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  3. Moikel

    Brandon Guest

    Try this:
    <SNIP>

    clock_proc: process
    begin
    if (now = 0 ns) then
    clk <= '0';
    end if;
    wait for 25 ns;
    clk <= '1';
    wait for 5 ns;
    clk <= '0';

    end process clock_proc;

    </SNIP>

    -Brandon
    Brandon, Mar 8, 2006
    #3
  4. Moikel

    Andy Guest

    How about:

    signal clock : std_logic := '0';

    ....

    clock <= '1' after 25 ns when clock = '0'
    else '0' after 5 ns when clock = '1';

    Andy Jones
    Andy, Mar 9, 2006
    #4
  5. Moikel

    anupam Guest

    how about......

    clock:process
    clock<='1';
    wait for 5 ns;
    clock <='0';
    wait for 25 ns;
    end process clock;


    regards,
    Anupam Jain
    anupam, Mar 9, 2006
    #5
  6. Moikel

    Guest

    Moikel did not mention at all
    if it is for simulation or for synthesis ...
    , Mar 9, 2006
    #6
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