Combined AFTER and WHEN statement

[JB]

Hi folks,

I'm stuggling with a problem using the following VHDL syntax:

<target_signal> <= <value_0> WHEN <condition_0> ELSE
<value_1> AFTER <delay_1> WHEN
<condition_1> ELSE
<value_2> AFTER <delay_2> WHEN
<condition_2> ELSE
...
<value_n>;

My testbench was working well with modelsim 6.5. But my client wan't
me to use modelsim 6.3, so I tried running it on that version and
BOOM:
This statement generates 'X' result on my target signal when one of
the <condition_x> is true.

Is this statement valid VHDL? or is modelsim 6.3 erroneous ?

Thanks in adavance.

 

[hssig]

Hi,
I have tried the following test with Modelsim PE 10.0b, no problems.


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity test_when is
end entity;

architecture test of test_when is
signal clk : std_logic := '0';
signal cnt : unsigned(2 downto 0) := (others => '0');
signal sig : std_logic := 'X';
begin
clk <= (not clk) after 10 ns;

cnt <= cnt + 1 when rising_edge(clk);

sig <= '1' when cnt="000" else '0' after 1.5 ns when cnt="001"
else 'Z' after 1.5 ns when cnt="010"
else 'H';
end architecture;



Cheers, hssig