Compiling Error : "Value of index is not static"

Discussion in 'VHDL' started by andrew_ross, Nov 10, 2008.

  1. andrew_ross

    andrew_ross

    Joined:
    Nov 6, 2008
    Messages:
    6
    Hi,
    I'm implementing a simple ripple carry adder using instances of a simple adder (called CLA...that works..).The ripple carry adder is generic , N is the bit widht.
    Unfortunately when I loop to generate the simple adders ("CLA" components..) ,
    I receive 2 errors : value "I" is not static (at the component "as": entity) , and value of index is not static(at aLess1: entity) .


    Code (Text):
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    use IEEE.STD_LOGIC_ARITH.ALL;
    use IEEE.STD_LOGIC_UNSIGNED.ALL;


    entity RCA is
         
         generic(N:integer:=4);

        Port ( A : in  STD_LOGIC_VECTOR(N-1 downto 0);--nel caso da 3 a 0 (cio√® 4)
               B : in  STD_LOGIC_VECTOR(N-1 downto 0);
               S : out  STD_LOGIC_VECTOR(N-1 downto 0);
               Carry_in : in  STD_LOGIC;--un solo bit di uscita globale
               Carry_out : out  STD_LOGIC);--un solo bit di uscita globale
    end RCA;

    architecture behavioral of RCA is
     
      signal c : std_logic_vector(N-1 to 0); -- internal carry signal

    COMPONENT  CLA --
       
            GENERIC (N: INTEGER := 32);  

        PORT (  a     : IN  UNSIGNED ((N-1) DOWNTO 0);
                    b       : IN    UNSIGNED ((N-1) DOWNTO 0);             
                    c_in    : IN    STD_LOGIC;
                    s       : OUT   UNSIGNED ((N-1) DOWNTO 0);
                    c_out   : OUT   STD_LOGIC;
                    overflow   : OUT STD_LOGIC
             
                );
        END COMPONENT;
       
       
       
       

    begin

      a0: entity CLA generic map(1) port map(A(0)=>a(0),B(0)=>b(0),C_in=>Carry_in,C_out=>c(0),S(0)=>S(0));
     
     
      middle: for I in 1 to N-2 generate
                   
                as: entity CLA generic map(1) port map(A(I)=>a(I),B(I)=>b(I),C_in=> c(I-1),C_out=>c(I), S(I)=>s(I));
             
                end generate middle;
               
               
     
      aLess1: entity CLA generic map(1) port map(A(N-1)=>a(N-1),B(N-1)=>b(N-1),C_in=> c(N-2) ,C_out=>Carry_out,S(N-1)=>s(N-1));



    end Behavioral;

     
    Could you help me please?
    Thanks a lot in advance..
     
    andrew_ross, Nov 10, 2008
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  2. andrew_ross

    jeppe

    Joined:
    Mar 10, 2008
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    Denmark
    How come your having two different values of the Generic N?

    Are your planning to implement this in a FPGA?
     
    jeppe, Nov 10, 2008
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  3. andrew_ross

    andrew_ross

    Joined:
    Nov 6, 2008
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    Just because COMPONENT CLA is a module itself implemented with generics..xilinx compiler apparently don't get any errors for that..

    I have to implementit to fpga spartan III
     
    andrew_ross, Nov 10, 2008
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