Conditional Check on Vectors

Discussion in 'VHDL' started by Analog Guy, Oct 6, 2004.

  1. Analog Guy

    Analog Guy Guest

    As part of my testbench, I want to verify that unused I/O are tri-stated (as
    per design). Some of the
    unused I/O are vectors, specified as STD_LOGIC_VECTOR with various sizes.

    I want to do a PROCEDURE call, to evaluate the given output vectors, which
    may be of varying
    sizes.

    I tried the following with no success: IF (test = (OTHERS => 'Z')) THEN,
    where test is STD_LOGIC_VECTOR.

    Per my search of the newsgroup, I tried: IF (test = (test'RANGE => 'Z'))
    THEN

    Although this compiled without any errors, it doesn't actually work in my
    testbench simulation.
    If test is specified as STD_LOGIC_VECTOR(2 DOWNTO 0), I observe the
    following results:

    Vector PASS/FAIL
    ------ --------------
    "ZZZ" PASS
    "111" FAIL
    "Z11" PASS ????????
    "1Z1" PASS ?????????
    etc.

    How are these vectors passing this conditional statement? Can I not check
    the whole vector at once, or do I have
    to check element by element?

    I'd appreciate any insight.
     
    Analog Guy, Oct 6, 2004
    #1
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  2. On Tue, 5 Oct 2004 22:32:46 -0400, "Analog Guy" <>
    wrote:

    >As part of my testbench, I want to verify that unused I/O are tri-stated (as
    >per design). Some of the
    >unused I/O are vectors, specified as STD_LOGIC_VECTOR with various sizes.


    An alternative approach would be to weakly drive the I/O bus from your
    testbench (i.e. with 'H' then 'L' instead of '1' then '0') and see what
    you get. Tri-stated elements will be resolved to the weak drive signal,
    others will not.

    This approach would also work in hardware, while testing for 'Z'
    obviously will not!

    - Brian
     
    Brian Drummond, Oct 6, 2004
    #2
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  3. Analog Guy

    Analog Guy Guest

    "Analog Guy" <> wrote in message news:<eLI8d.11180$>...
    > As part of my testbench, I want to verify that unused I/O are tri-stated (as
    > per design). Some of the
    > unused I/O are vectors, specified as STD_LOGIC_VECTOR with various sizes.
    >
    > I want to do a PROCEDURE call, to evaluate the given output vectors, which
    > may be of varying
    > sizes.
    >
    > I tried the following with no success: IF (test = (OTHERS => 'Z')) THEN,
    > where test is STD_LOGIC_VECTOR.
    >
    > Per my search of the newsgroup, I tried: IF (test = (test'RANGE => 'Z'))
    > THEN
    >
    > Although this compiled without any errors, it doesn't actually work in my
    > testbench simulation.
    > If test is specified as STD_LOGIC_VECTOR(2 DOWNTO 0), I observe the
    > following results:
    >
    > Vector PASS/FAIL
    > ------ --------------
    > "ZZZ" PASS
    > "111" FAIL
    > "Z11" PASS ????????
    > "1Z1" PASS ?????????
    > etc.
    >
    > How are these vectors passing this conditional statement? Can I not check
    > the whole vector at once, or do I have
    > to check element by element?
    >
    > I'd appreciate any insight.



    The actual warning message from ModelSim is:

    # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic
    operand, the result will be 'X'(es).
     
    Analog Guy, Oct 6, 2004
    #3
  4. Analog Guy wrote:

    >>Per my search of the newsgroup, I tried: IF (test = (test'RANGE => 'Z'))
    >>THEN

    >
    > The actual warning message from ModelSim is:
    >
    > # ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic
    > operand, the result will be 'X'(es).


    You might see this warning, but it is not caused by the IF statement, as
    it does not contain any arithmetic operand.

    To get the line number in the warning message, put the following in your
    modelsim.ini file (one line):

    AssertionFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I File:
    %F Line: %L\n\n"

    It's probably already there, commented out.

    As for your original question: the test should work, but you must be
    sure that there are no other drivers overriding the Z value of any bit.

    Paul.
     
    Paul Uiterlinden, Oct 7, 2004
    #4
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