conv N/A _ with_Virtex5

Discussion in 'VHDL' started by Salah Kortli, Apr 23, 2014.

  1. Salah Kortli

    Salah Kortli Guest

    Hello world

    I just use a low frequency sinusoidal signals, the frequency range of alternative reports will be about 2 Hz. I want to clock the FPGA to manage the reports.
    I think I need to reduce or divide the frequency of the clock signals to 2 Hz to 1MHz. Then comes the use of Digital / Analog converter DAC.

    Is it possible to go down to values mHz. Will he links, tutorials, etc ... that guides me to it.


    cordially
     
    Salah Kortli, Apr 23, 2014
    #1
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