counters in fsm

Discussion in 'VHDL' started by DualCore, Feb 8, 2007.

  1. DualCore

    DualCore

    Joined:
    Sep 27, 2006
    Messages:
    4
    i am trying to increment value of 4-bit counter in fsm , but instead of bin 01 its adding 02 and although the state advancement if on every risiing edge of clk , this counter is incrementing on falling edge as well , i tried using a procedure instead and calling a procedure , but to same effect , any clues ???
    any one ???
     
    DualCore, Feb 8, 2007
    #1
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  2. DualCore

    rgurrola

    Joined:
    Nov 19, 2006
    Messages:
    4
    hope this works for you!!!

    here is what I have used in the past and it has worked fine. Its from VHDL- online main frame

    good luck

    RG


    Library IEEE;
    use IEEE.Std_Logic_1164.all;

    entity COUNTER is
    port ( CLK : in std_ulogic;
    Q : out integer range 0 to 15 );
    end COUNTER;

    architecture A of COUNTER is
    signal COUNT : integer range 0 to 15 ;
    begin
    process (CLK)
    begin
    if CLK`event and CLK = `1` then
    if (COUNT >= 9) then
    COUNT <= 0;
    else
    COUNT <= COUNT +1;
    end if;
    end if;
    end process;
    Q <= COUNT;
    end A;
     
    rgurrola, Feb 20, 2007
    #2
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  3. DualCore

    rgurrola

    Joined:
    Nov 19, 2006
    Messages:
    4
    I have used this in the past I hope it works for you!!
    you will have to modify it to fit your needs. This was taken frm VHDL-Online Main frame

    rg


    Library IEEE;
    use IEEE.Std_Logic_1164.all;

    entity COUNTER is
    port ( CLK : in std_ulogic;
    Q : out integer range 0 to 15 );
    end COUNTER;

    architecture A of COUNTER is
    signal COUNT : integer range 0 to 15 ;
    begin
    process (CLK)
    begin
    if CLK`event and CLK = `1` then
    if (COUNT >= 9) then
    COUNT <= 0;
    else
    COUNT <= COUNT +1;
    end if;
    end if;
    end process;
    Q <= COUNT;
    end A;
     
    Last edited: Feb 20, 2007
    rgurrola, Feb 20, 2007
    #3
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