counters in fsm

[DualCore]

i am trying to increment value of 4-bit counter in fsm , but instead of bin 01 its adding 02 and although the state advancement if on every risiing edge of clk , this counter is incrementing on falling edge as well , i tried using a procedure instead and calling a procedure , but to same effect , any clues ???
any one ???

 

[rgurrola]

hope this works for you!!!

here is what I have used in the past and it has worked fine. Its from VHDL- online main frame

good luck

RG


Library IEEE;
use IEEE.Std_Logic_1164.all;

entity COUNTER is
port ( CLK : in std_ulogic;
Q : out integer range 0 to 15 );
end COUNTER;

architecture A of COUNTER is
signal COUNT : integer range 0 to 15 ;
begin
process (CLK)
begin
if CLK`event and CLK = `1` then
if (COUNT >= 9) then
COUNT <= 0;
else
COUNT <= COUNT +1;
end if;
end if;
end process;
Q <= COUNT;
end A;

 

[rgurrola]

I have used this in the past I hope it works for you!!
you will have to modify it to fit your needs. This was taken frm VHDL-Online Main frame

rg


Library IEEE;
use IEEE.Std_Logic_1164.all;

entity COUNTER is
port ( CLK : in std_ulogic;
Q : out integer range 0 to 15 );
end COUNTER;

architecture A of COUNTER is
signal COUNT : integer range 0 to 15 ;
begin
process (CLK)
begin
if CLK`event and CLK = `1` then
if (COUNT >= 9) then
COUNT <= 0;
else
COUNT <= COUNT +1;
end if;
end if;
end process;
Q <= COUNT;
end A;