A
AndyAtHome
Hi All,
I've only been using ISE & Modelsim for 3 weeks - a frustrating three
weeks - so forgive me if this is simple and/or dumb question but I
can't seem to find it posted previously or in the FAQ.
I've got to the point where I want to start writing my own test
benches, rather simply using the HDL bencher tool - among other things
I want read test vectors in from a file.
So I generated a testbench within ISE using the waveform window to
create a template as starting point. I opened the resulting .vhw file
that was generated by HDL bencher and as suggested in the comments at
the top of the .vhw file, saved it as a .vhd file and added it to my
project in ISE as a test bench - in preperation for modifying it to
my requirements.
Great, only now I can't check the syntax of the file ! .... there
isn't an option in the process window. I can vcom the file from with
Modelsim of course - but is this the best way to develop a test bench?
This doesn't seem very practical to me.
In ISE I also tried adding the .vhd testbench file as a normal VHDL
module, I can now check the syntax but when I do ISE errors with
"Wait for statement unsupported" as the testbench has lots of these
statement for clock generation and timed data input.
Where do I go from here?
Thanks,
Andy.
I've only been using ISE & Modelsim for 3 weeks - a frustrating three
weeks - so forgive me if this is simple and/or dumb question but I
can't seem to find it posted previously or in the FAQ.
I've got to the point where I want to start writing my own test
benches, rather simply using the HDL bencher tool - among other things
I want read test vectors in from a file.
So I generated a testbench within ISE using the waveform window to
create a template as starting point. I opened the resulting .vhw file
that was generated by HDL bencher and as suggested in the comments at
the top of the .vhw file, saved it as a .vhd file and added it to my
project in ISE as a test bench - in preperation for modifying it to
my requirements.
Great, only now I can't check the syntax of the file ! .... there
isn't an option in the process window. I can vcom the file from with
Modelsim of course - but is this the best way to develop a test bench?
This doesn't seem very practical to me.
In ISE I also tried adding the .vhd testbench file as a normal VHDL
module, I can now check the syntax but when I do ISE errors with
"Wait for statement unsupported" as the testbench has lots of these
statement for clock generation and timed data input.
Where do I go from here?
Thanks,
Andy.