Driving 1 bit off 2 clocks

Discussion in 'VHDL' started by snooks, Mar 24, 2008.

  1. snooks

    snooks

    Joined:
    Mar 24, 2008
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    I am working on implementing the MC6850 ACIA for academic purposes. The implementation requires that when data is written to the data register, the empty flag is set to zero and when the data is read from the register, it is set to 1 (to indicate empty).

    The reading and writing are 2 different processes and I am not allowed to modify this same empty bit by 2 different processes. I am not sure how exactly to set this bit properly. Would somebody here be able to provide any advice? I'd really appreciate it.

    Thank you,

    Snooks
     
    snooks, Mar 24, 2008
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  2. snooks

    jeppe

    Joined:
    Mar 10, 2008
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    Indeed - your not allowed to modify the same bit from two or more processes.

    Your solution should be based on one process which uses asynchronous clear to modifify the bit (0 or 1) and clockes the oppersite value on eighter rising or falling edge.

    Its your own chooise how this should be done.

    An alternative solution could be to let the E-Clock (your system clock) trigger the F/F and then decide which value should be transfered (or the value should be kept)

    Hope you got the meaning of this.

    Your welcome
    Jeppe
     
    jeppe, Mar 24, 2008
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  3. snooks

    snooks

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    Thanks again for your reply. I think I'll use the first approach you suggested and put everything into 1 process. I'll post here if I succeed :).

    Thanks again,
    Sihanook
     
    snooks, Mar 24, 2008
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