FATAL_ERROR:Xst:xstedge.c:128:1.4 ???

Discussion in 'VHDL' started by Mich, May 26, 2005.

  1. Mich

    Mich Guest

    Hi
    I 'm programming something and with this code I don't get any error

    tel := tel +1;
    if (tel = 4) then
    tel := 0;
    rico := rico + 20;

    if (rico = 100) then
    rico := 0;
    som := 0;
    end if;


    end if;

    som := som + rico;

    klx := 170;
    grx := 190;


    if (x_pos > klx and x_pos < grx) then
    if (y_pos > 240 and y_pos < 260) then
    sec_tek <= '1';
    else
    sec_tek <= '0';
    end if;
    else
    sec_tek <= '0';
    end if;


    but when I change

    klx := 170;
    grx := 190;

    to

    klx := 170 + som;
    grx := 190 + som;

    I get this error message

    FATAL_ERROR:Xst:xstedge.c:128:1.4 - Signal tekensec_main_som<0> has no
    source after simplification. This may be due to a non load
    combinatorial loop. Process will terminate. To resolve this error,
    please consult the Answers Database and other online resources at
    http://support.xilinx.com. If you need further assistance, please open
    a Webcase by clicking on the "WebCase" link at
    http://support.xilinx.com


    Can somebody help me?

    Mich
     
    Mich, May 26, 2005
    #1
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  2. Mich

    Neo Guest

    cant be sure without the whole process block but try using "rico"
    instead of "som" as its anyhow optimized.
     
    Neo, May 27, 2005
    #2
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  3. Mich

    Andy Peters Guest

    Mich wrote:
    > Hi
    > I 'm programming something and with this code I don't get any error
    >
    > tel := tel +1;
    > if (tel = 4) then
    > tel := 0;
    > rico := rico + 20;
    >
    > if (rico = 100) then
    > rico := 0;
    > som := 0;
    > end if;
    >
    >
    > end if;
    >
    > som := som + rico;
    >
    > klx := 170;
    > grx := 190;
    >
    >
    > if (x_pos > klx and x_pos < grx) then
    > if (y_pos > 240 and y_pos < 260) then
    > sec_tek <= '1';
    > else
    > sec_tek <= '0';
    > end if;
    > else
    > sec_tek <= '0';
    > end if;
    >
    >
    > but when I change
    >
    > klx := 170;
    > grx := 190;
    >
    > to
    >
    > klx := 170 + som;
    > grx := 190 + som;
    >
    > I get this error message
    >
    > FATAL_ERROR:Xst:xstedge.c:128:1.4 - Signal tekensec_main_som<0> has no
    > source after simplification. This may be due to a non load
    > combinatorial loop. Process will terminate. To resolve this error,
    > please consult the Answers Database and other online resources at
    > http://support.xilinx.com. If you need further assistance, please open
    > a Webcase by clicking on the "WebCase" link at
    > http://support.xilinx.com
    >
    > Can somebody help me?


    Looks like you're a software guy trying to implement hardware ...
    you've written a huge combinatorial loop.

    -a
     
    Andy Peters, May 27, 2005
    #3
  4. Mich

    Mich Guest

    I know
    but the strange thing it
    it seams that klx and grx does not change
    how is this ^possible?

    Mich
     
    Mich, May 29, 2005
    #4
  5. Mich

    Mich Guest

    I know
    but the strange thing it
    it seams that klx and grx does not change
    how is this ^possible?

    tomorrow I 'm back at school and post all the code

    Mich
     
    Mich, May 29, 2005
    #5
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