fixed point syntax question

Discussion in 'VHDL' started by sanborne, Dec 11, 2008.

  1. sanborne

    sanborne Guest

    I cannot figure out what the problem is in the following code:

    -- begin code
    library ieee_proposed;
    use ieee_proposed.std_logic_1164_additions.all;
    use ieee_proposed.math_utility_pkg.all;
    use ieee_proposed.fixed_pkg.all;

    library ieee;
    use ieee.numeric_std.all;

    entity test is

    port (
    a : in unsigned(31 downto 0);
    x : out sfixed(1 downto -30));

    end test;

    architecture imp1 of test is
    begin -- imp1
    --the following works:
    -- x <= resize(sfixed(a) * to_sfixed(0.5,0,-1), 1, -30);

    --this does not...I need to be able to control the rounding and
    overflow behavior
    x <= resize(sfixed(a) * to_sfixed(0.5,0,-1), 1, -30, true, false);

    end imp1;
    -- end code

    I expect that this is an easy problem, but the error the ModelSim
    compiler gives is that there is no feasible subprogram "resize". The
    syntax above is definitely in the documentation, and I have found some
    examples online also. Any thoughts? Is it a problem with my conversion
    from the unsigned input? But then why would the code that is commented
    out compile? I would sure like to understand this.

    SY
    sanborne, Dec 11, 2008
    #1
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  2. sanborne

    KJ Guest

    "sanborne" <> wrote in message
    news:...
    >I cannot figure out what the problem is in the following code:
    > --the following works:
    > -- x <= resize(sfixed(a) * to_sfixed(0.5,0,-1), 1, -30);
    >
    > --this does not...I need to be able to control the rounding and
    > overflow behavior
    > x <= resize(sfixed(a) * to_sfixed(0.5,0,-1), 1, -30, true, false);
    >


    The last two parameters to resize are not booleans. Your choices are

    type fixed_round_style_type is (fixed_round, fixed_truncate);

    type fixed_overflow_style_type is (fixed_saturate, fixed_wrap);

    Kevin Jennings
    KJ, Dec 11, 2008
    #2
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