sfixed in generics

Discussion in 'VHDL' started by Paul, Jul 8, 2010.

  1. Paul

    Paul Guest

    Hi,

    in the example attached I did try to parametrize my fir filter (direct
    form I second order structure) internal signals. Modelsim complains on
    it and I have no idea why and how to fix it. Anyway, the idea behind
    should be clear.

    Thanks,
    Olaf


    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;

    library floatfixlib;
    use floatfixlib.math_utility_pkg.all; -- ieee_proposed for VHDL-93 version
    use floatfixlib.fixed_pkg.all; -- ieee_proposed for compatibility version

    entity df1tsos is

    generic(
    numerator: sfixed := sfixed(16 downto -14); -- [-2 2)
    denominator: sfixed := sfixed(16 downto -14); -- [-2 2)
    numerator_state: sfixed := sfixed(16 downto -12); -- [-8 8)
    denominator_state: sfixed := sfixed(16 downto -12) -- [-8 8)
    );

    port (
    clk : in std_ulogic;
    clk_en : in std_ulogic;
    reset : in std_ulogic;
    input : in sfixed(16 downto -14); -- [-2 2)
    output : out sfixed(16 downto -14) -- [-2 2)
    );

    end entity df1tsos;


    architecture rtl of df1tsos is

    subtype numerator_type is sfixed range numerator'high downto
    numerator'low;

    begin


    end architecture rtl;
    Paul, Jul 8, 2010
    #1
    1. Advertising

  2. Paul

    Tricky Guest

    On 8 July, 13:27, Paul <> wrote:
    > Hi,
    >
    > in the example attached I did try to parametrize my fir filter (direct
    > form I second order structure) internal signals. Modelsim complains on
    > it and I have no idea why and how to fix it. Anyway, the idea behind
    > should be clear.
    >
    > Thanks,
    > Olaf
    >
    > library ieee;
    > use ieee.std_logic_1164.all;
    > use ieee.numeric_std.all;
    >
    > library floatfixlib;
    > use floatfixlib.math_utility_pkg.all; -- ieee_proposed for VHDL-93 version
    > use floatfixlib.fixed_pkg.all; -- ieee_proposed for compatibility version
    >
    > entity df1tsos is
    >
    >   generic(
    >     numerator:          sfixed  := sfixed(16 downto -14);  -- [-2 2)
    >     denominator:        sfixed  := sfixed(16 downto -14);  -- [-2 2)
    >     numerator_state:    sfixed  := sfixed(16 downto -12);  -- [-8 8)
    >     denominator_state:  sfixed  := sfixed(16 downto -12)   -- [-8 8)
    >   );
    >
    >   port (
    >     clk       : in  std_ulogic;
    >     clk_en    : in  std_ulogic;
    >     reset     : in  std_ulogic;
    >     input     : in  sfixed(16 downto -14);  -- [-2 2)
    >     output    : out sfixed(16 downto -14)   -- [-2 2)
    >   );
    >
    > end entity df1tsos;
    >
    > architecture rtl of df1tsos is
    >
    >   subtype numerator_type is sfixed range numerator'high downto
    > numerator'low;
    >
    > begin
    >
    > end architecture rtl;


    Generics are really constants. What you've done is try defined a load
    of types as generics, which isnt allowed up to VHDL 2002. you would be
    able to do it in VHDL 2008 (but not like you've done it), but its not
    really supported by anyone in any detail yet. You'll have to change
    the generics to things like:

    generic (
    numerator_high : integer := 16;
    numerator_low : integer := -14;
    ....etc
    Tricky, Jul 8, 2010
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Willem Oosthuizen
    Replies:
    1
    Views:
    2,782
    Jonathan Bromley
    Jul 9, 2003
  2. Acciduzzu

    Integers only as generics?

    Acciduzzu, Sep 22, 2003, in forum: VHDL
    Replies:
    4
    Views:
    717
    Allan Herriman
    Sep 23, 2003
  3. Juergen Berchtel
    Replies:
    1
    Views:
    5,990
    John C. Bollinger
    May 20, 2005
  4. Soul
    Replies:
    0
    Views:
    518
  5. Paul
    Replies:
    5
    Views:
    720
Loading...

Share This Page