floating point divider

[john]

hi,

my main clock is 100 Mhz and I need to lower it downto 1Mhz. I tired
to do that with the clock divider but getting 1.5Mhz clock. I need
some floating point division to get exactly 1Mhz. can any body advice
me that how to proceed?

Thanks
John

 

[Mike Treseler]

my main clock is 100 Mhz and I need to lower it downto 1Mhz. I tired
to do that with the clock divider but getting 1.5Mhz clock. I need
some floating point division to get exactly 1Mhz. can any body advice
me that how to proceed?

I would leave my main clock at 100 Mhz
and create a synchronous clock enable
for the slow process. For power
of 2 dividers, all I can use the msb
of a prescale counter like
the "clk enable counters" example here.

http://home.comcast.net/~mike_treseler/

For a non-power-of-two divider I could
generalize the prescaler to count
by a larger increment, say

my_divider_ratio * 2**n

where n is large enough to cover
the required divider accuracy.

-- Mike Treseler

 

[KJ]

hi,

my main clock is 100 Mhz and I need to lower it downto 1Mhz. I tired
to do that with the clock divider but getting 1.5Mhz clock. I need
some floating point division to get exactly 1Mhz. can any body advice
me that how to proceed?

1. Create a counter that counts from 0 to 99 (and then goes back to 0).
(i.e. if (Count = 99) then Count <= 0 else Count <= Count + 1
2. Clock that counter with your 100 MHz clock
3. Pick off any particular count or range of counts to create whatever
signal it is you're trying to create. As an example, if you want a 50% duty
cycle 1MHz signal then you can do this in a number of ways....

My_Sig <= '1' when (Count > 50) else '0'; -- Concurrent statement
approach

-- Clocked process approach, sometimes takes fewer logic resources then the
concurrent statement approach
if rising_edge(clock) then
if (Count = 0) then
My_Sig <= '0';
elsif (Count = 50) then
My_Sig <= '1';
end if;
end if;

If you're creating this 1MHz clock for further use inside a PLD/FPGA then I
would suggest you do as Mike suggested and use 'My_Sig' not as a clock
itself but as a clock enable. If you really do need to create a 1MHz
"clock" for external use, then the above will do the trick.

Kevin Jennings

 

[Michael Jørgensen]

If you're creating this 1MHz clock for further use inside a PLD/FPGA then
I would suggest you do as Mike suggested and use 'My_Sig' not as a clock
itself but as a clock enable.

Hi, just one quick question from a learner. Why do you suggest against using
My_Sig as a clock signal itself? What difference does it make using it as a
clock enable?

-Michael.

 

[KJ]

Hi, just one quick question from a learner. Why do you suggest against
using My_Sig as a clock signal itself? What difference does it make using
it as a clock enable?

Because in most cases, the circuit (or code) that you want clocked by this
'new' clock signal will generate some output signal that then gets fed back
to some other circuit (or code) that gets clocked by the original clock
signal and you have difficulty meeting setup times. If you stick with a
single clock then you don't have this problem.

Remember that the clock signal to every flip flop has some skew associated
with it relative to whatever reference point you choose. This means that
every flip flop does not get clocked at 'exactly' the same time. The
FPGA/CPLD/ASIC vendors know this and have optomized their designs to the
point that they can guarantee that, while not stricly simultaneous, every
flip flop can talk to any other flip flop without violating setup/hold
requirements because the fitter will use the global clock resources to
distribute this clock. However, every flip flop also has a Tco which is the
time from when the clock switches until the output is valid. Even if the
clock could magically get distributed with absolutely zero skew, Tco will
never be 0. Any time you generate some internal clock and then use it to
clock something else you'll have at least two of these Tco delays (one to
generate the clock, the other for the Tco of the flop that is clocked by
this new clock). Start stacking these up and the outputs might not be able
to reliably be moved back into the original clock domain (which like I said
is frequently the case). None of this happens if you simply generate a one
clock cycle wide clock enable signal at the appropriate times.

Lastly, this technique is primarily intended for FPGA/CPLD/discrete parts
designs. Inside an ASIC you'll tend to do other things but that is because
in ASIC world, you have more explicit control and knowledge of routing
delays and can apply these asynchronous design techniques. They still have
to concern themselves with Tco and other delays but they also have more
control over them and can do something to address it....whereas in the FPGA
you pretty much can not do much other than 'hope'.

Kevin Jennings