FLOATING POINT DIVISION

Discussion in 'VHDL' started by sunwij, Dec 28, 2003.

  1. sunwij

    sunwij Guest

    Following is a portion of the code which calculates a rate of rain
    fall at a remote location and executes a specfic task if the rate
    exceeds a given threshold. Synopsis throws following error: "
    STANDARD.STD" package not found

    Am I missing any specific pkg. Tried http://www.eda.org/fphdl/
    read the whole page. None found. As a work around I am using a
    function to do division which uses lot of hardware.

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.numeric_std.all;
    use ieee.math_real.all;
    entity real_division is port ( rain_fall : in real;
    time_elapsed: in real;
    rain_rate: out real}
    end real_division;
    architecture myreal_division of real_division is

    Signal a1,b1 :real;

    begin

    a1<= rain_fall;
    b1<= time_elapsed;
    process (a1,b1)
    begin
    rain_rate <=a1/b1;

    end process;

    end real_division;
    sunwij, Dec 28, 2003
    #1
    1. Advertising

  2. sunwij

    David Bishop Guest

    sunwij wrote:
    > Following is a portion of the code which calculates a rate of rain
    > fall at a remote location and executes a specfic task if the rate
    > exceeds a given threshold. Synopsis throws following error: "
    > STANDARD.STD" package not found
    >
    > Am I missing any specific pkg. Tried http://www.eda.org/fphdl/
    > read the whole page. None found. As a work around I am using a
    > function to do division which uses lot of hardware.


    First off, "real" is not synthesizable, since it is implementation
    dependent (I know that that is fixed in vhdl-2000). In the floating
    point packages, I created a type called "fp32".
    Download "fphdl_base_pkg.vhd", "fphdl_base_pkg_body.vhd", and
    "fphdl32_pkg.vhd".

    > library ieee;
    > use ieee.std_logic_1164.all;
    > use ieee.numeric_std.all;
    > use ieee.math_real.all;


    replace this line with:
    use work.fphdl32_pkg.all;

    > entity real_division is port ( rain_fall : in real;
    > time_elapsed: in real;
    > rain_rate: out real}


    Change "real" to "fp32" (32 bit floating point number).

    > end real_division;
    > architecture myreal_division of real_division is
    >
    > Signal a1,b1 :real;


    Once again, "fp32".

    > begin
    >
    > a1<= rain_fall;
    > b1<= time_elapsed;
    > process (a1,b1)
    > begin
    > rain_rate <=a1/b1;
    >
    > end process;
    >
    > end real_division;


    Now this still won't work in Synopsys. Why? Synopsys can't do a
    divide that isn't a divide by 2.
    Not to worry. In "fphdl_base_pkg_body.vhd" you will find a synthesizable
    unsigned divide routine that will work fine with Synopsys.

    The downside here is that the divider will not be very fast. I have one
    that will work at 100 MHz in a "Xilinx" part if you want it.

    --
    NAME: David W. Bishop INTERNET:
    David Bishop, Dec 28, 2003
    #2
    1. Advertising

  3. sunwij

    sunwij Guest

    David Bishop <> wrote in message news:<DnEHb.84463$>...
    >
    > The downside here is that the divider will not be very fast. I have one
    > that will work at 100 MHz in a "Xilinx" part if you want it.


    Thanks so much for your valuble advise.

    Sunwij
    sunwij, Dec 29, 2003
    #3
  4. sunwij

    sunwij Guest

    David Bishop <> wrote in message news:<DnEHb.84463$>...
    >
    > The downside here is that the divider will not be very fast. I have one
    > that will work at 100 MHz in a "Xilinx" part if you want it.


    Is this "Xlinix" part is hardware or a VHDL code ? . Please give
    little more details. Thanks
    sunwij, Dec 29, 2003
    #4
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Pieter Hulshoff

    Floating point division

    Pieter Hulshoff, Dec 5, 2004, in forum: VHDL
    Replies:
    2
    Views:
    6,350
    Pieter Hulshoff
    Dec 7, 2004
  2. Derek Simmons

    Re: Floating Point Division

    Derek Simmons, May 9, 2010, in forum: VHDL
    Replies:
    1
    Views:
    1,056
    niyander
    May 9, 2010
  3. sajsajsajsaj

    VHDL code for floating point division

    sajsajsajsaj, Jun 5, 2011, in forum: VHDL
    Replies:
    0
    Views:
    1,414
    sajsajsajsaj
    Jun 5, 2011
  4. Saraswati lakki
    Replies:
    0
    Views:
    1,321
    Saraswati lakki
    Jan 6, 2012
  5. Michael Neumann
    Replies:
    29
    Views:
    351
    Michael Neumann
    Jun 11, 2004
Loading...

Share This Page