FPGA stepping level

[naliali]

Hi all,


after "place& rout", XST sends the below message:
"This design is using the default stepping level (major silicon
revision) for this device (1). Unless your design is targeted at
devices of this stepping level, it is ecommended that you explicitly
specify the stepping level of the parts you will be using. . . . ."

Does anybody know how to specify the stepping level of a xilinx FPGA.
and how it can impact the performance of design?

regards

 

[ghelbig]

Hi all,

after "place& rout", XST sends the below message:
"This design is using the default stepping level (major silicon
revision) for this device (1). Unless your design is targeted at
devices of this stepping level, it is ecommended that you explicitly
specify the stepping level of the parts you will be using. . . . ."

Does anybody know how to specify the stepping level of a xilinx FPGA.
and how it can impact the performance of design?

regards

You specify the stepping level in the same menu you select the chip.

Early steppings of an FPGA may have known deficiencies that the
synthesizer will work around. Later steppings may have changes that
require a change in the bit stream. And other reasons.

G.

 

[naliali]

You specify the stepping level in the same menu you select the chip.

Early steppings of an FPGA may have known deficiencies that the
synthesizer will work around. Later steppings may have changes that
require a change in the bit stream. And other reasons.

G.

"You specify the stepping level in the same menu you select the chip."
but that is the "speed grade" not stepping level, it needs a bit more
manipulating desin.