FPGA stepping level

Discussion in 'VHDL' started by naliali, Aug 13, 2007.

  1. naliali

    naliali Guest

    Hi all,


    after "place& rout", XST sends the below message:
    "This design is using the default stepping level (major silicon
    revision) for this device (1). Unless your design is targeted at
    devices of this stepping level, it is ecommended that you explicitly
    specify the stepping level of the parts you will be using. . . . ."

    Does anybody know how to specify the stepping level of a xilinx FPGA.
    and how it can impact the performance of design?

    regards
     
    naliali, Aug 13, 2007
    #1
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  2. naliali

    Guest

    On Aug 13, 5:56 am, naliali <> wrote:
    > Hi all,
    >
    > after "place& rout", XST sends the below message:
    > "This design is using the default stepping level (major silicon
    > revision) for this device (1). Unless your design is targeted at
    > devices of this stepping level, it is ecommended that you explicitly
    > specify the stepping level of the parts you will be using. . . . ."
    >
    > Does anybody know how to specify the stepping level of a xilinx FPGA.
    > and how it can impact the performance of design?
    >
    > regards


    You specify the stepping level in the same menu you select the chip.

    Early steppings of an FPGA may have known deficiencies that the
    synthesizer will work around. Later steppings may have changes that
    require a change in the bit stream. And other reasons.

    G.
     
    , Aug 14, 2007
    #2
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  3. naliali

    naliali Guest

    On Aug 14, 7:00 am, wrote:
    > On Aug 13, 5:56 am, naliali <> wrote:
    >
    > > Hi all,

    >
    > > after "place& rout", XST sends the below message:
    > > "This design is using the default stepping level (major silicon
    > > revision) for this device (1). Unless your design is targeted at
    > > devices of this stepping level, it is ecommended that you explicitly
    > > specify the stepping level of the parts you will be using. . . . ."

    >
    > > Does anybody know how to specify the stepping level of a xilinx FPGA.
    > > and how it can impact the performance of design?

    >
    > > regards

    >
    > You specify the stepping level in the same menu you select the chip.
    >
    > Early steppings of an FPGA may have known deficiencies that the
    > synthesizer will work around. Later steppings may have changes that
    > require a change in the bit stream. And other reasons.
    >
    > G.


    "You specify the stepping level in the same menu you select the chip."
    but that is the "speed grade" not stepping level, it needs a bit more
    manipulating desin.
     
    naliali, Aug 14, 2007
    #3
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