Functional VHDL Simulation Problem with Altera dual clock fifo

Discussion in 'VHDL' started by Thomas Fischer, Apr 9, 2005.

  1. Altera Modelsim 5.8e

    I'm new to modelsim and try to make a functional simulation for a
    project with an
    Altera Fifo (dcfifo).

    I get the following simulation error:
    last value in fifo cannot be read, rdempty flag toggles when last
    value is tried to read.

    the problem only occures, if a signal is used as the rdclk,
    if the rdclk is taken directly from the entity port clk_i everything
    works fine.

    ...
    ...
    begin

    txf_rdclk <= clk_i; -- problem if txf_rdclk is used in port map

    txfifo : dcfifo0
    PORT MAP (
    wrclk => wrclk_i,
    rdreq => txf_rdreq,
    aclr => rst_i,
    rdclk => txf_rdclk, -- problem if txf_rdclk is used in port map
    -- rdclk => clk_i, -- this works fine
    wrreq => wrreq_i,
    data => data_i,
    rdfull => txf_rdfull,
    rdempty => txf_rdempty,
    wrusedw => txf_wrusedw,
    wrfull => txf_wrfull_o,
    wrempty => txf_wrempty,
    q => txf_q,
    rdusedw => txf_rdusedw
    );
    ...
    ...

    why does i have problems with the signal txf_rdclk ?
    Thomas Fischer, Apr 9, 2005
    #1
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  2. Thomas Fischer schrieb:
    > Altera Modelsim 5.8e
    >
    > I'm new to modelsim and try to make a functional simulation for a
    > project with an
    > Altera Fifo (dcfifo).
    >
    > I get the following simulation error:
    > last value in fifo cannot be read, rdempty flag toggles when last
    > value is tried to read.
    >
    > the problem only occures, if a signal is used as the rdclk,
    > if the rdclk is taken directly from the entity port clk_i everything
    > works fine.
    >
    > ..
    > ..
    > begin
    >
    > txf_rdclk <= clk_i; -- problem if txf_rdclk is used in port map
    >
    > txfifo : dcfifo0
    > PORT MAP (
    > wrclk => wrclk_i,
    > rdreq => txf_rdreq,
    > aclr => rst_i,
    > rdclk => txf_rdclk, -- problem if txf_rdclk is used in port map
    > -- rdclk => clk_i, -- this works fine
    > wrreq => wrreq_i,
    > data => data_i,
    > rdfull => txf_rdfull,
    > rdempty => txf_rdempty,
    > wrusedw => txf_wrusedw,
    > wrfull => txf_wrfull_o,
    > wrempty => txf_wrempty,
    > q => txf_q,
    > rdusedw => txf_rdusedw
    > );
    > ..
    > ..
    >
    > why does i have problems with the signal txf_rdclk ?


    I'm still learning, seems to be some sort of "delta cycle race condition"
    Thomas Fischer, Apr 9, 2005
    #2
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  3. Thomas Fischer wrote:
    > Thomas Fischer schrieb:
    >
    >> the problem only occures, if a signal is used as the rdclk, if the
    >> rdclk is taken directly from the entity port clk_i everything
    >> works fine.

    >
    > I'm still learning, seems to be some sort of "delta cycle race condition"


    It is not a race condition in the sense of the definition of a race
    condition. The outcome is determinitic because it does not depend of the
    order of evaluation of processes (including signal assignments).

    Each signal assignment adds a delta cycle delay. By adding a signal
    assignment in the clock, the receiving block is clocked one delta cycle
    later. The effect of this is that it clocks in the new signal values
    (after the clock edge) of sending blocks running on the original clock
    (without the extra signal assgnment).

    In general it is a bad idea to put signal assignments in clocks. Or you
    must make sure that all clocks derived from a common clock source
    contain the same number of signal assignments.

    Some other solutions are discussed in
    http://verificationguild.com/modules.php?name=Forums&file=viewtopic&p=1765

    Paul.
    Paul Uiterlinden, Apr 11, 2005
    #3
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