Generate????

Discussion in 'VHDL' started by barbablu, Nov 16, 2004.

  1. barbablu

    barbablu Guest

    Hi,
    every time i try to use the FOR-GENERATE statement whit a gruop of signals i
    have the error LOOP expected. Can i use this statement for repetitive code
    with signals or i have to use only whit components?

    Thanks.
     
    barbablu, Nov 16, 2004
    #1
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  2. barbablu a écrit:
    > Hi,
    > every time i try to use the FOR-GENERATE statement whit a gruop of signals i
    > have the error LOOP expected. Can i use this statement for repetitive code
    > with signals or i have to use only whit components?


    Just don't use it inside a process.

    --
    ____ _ __ ___
    | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le -
    | | | | | (_| |_| | Invalid return address: remove the -
    |_| |_|_|\__|\___/
     
    Nicolas Matringe, Nov 16, 2004
    #2
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  3. You can generate using any complete process,
    as a base. This includes code templates,
    or instances. Maybe your error is coming
    from the base process code.

    Try compiling a design entity with a
    single base process with constant i
    first. Once this is debugged, put it inside

    make_processes: for i in 1 to 8 generate
    <insert debugged process using i here>
    end generate make_processes;


    -- Mike Treseler
     
    mike_treseler, Nov 16, 2004
    #3
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