if generate causes conflicts

Discussion in 'VHDL' started by janeruth, Oct 19, 2010.

  1. janeruth

    janeruth

    Joined:
    Jul 23, 2009
    Messages:
    9
    Hi all,

    Could someone shed some light on this for me, I have 2 mutually exclusive if generate statements inside 2 nested for generate loops, the indices of which form the if statement conditions. However, for some reason the simulator doesn't appear to evaluate the if's as mutually exclusive and I end up with conflicting signals.

    Code:
    lable1:for i in 0 to PARAMETER generate
    begin
    	lable2:for j in 0 to PARAMETER generate
    	begin
    		lable4: if (j > i) generate	
    			begin
    				an_in_array(j-1) <= out_arrayA(j);
    			end generate;
    
    		lable5: if (j<i) generate	
    			begin
    				an_in_array(j) <= out_arrayA(j);
    			end generate;
    		end generate;
    	end generate;
    
    	in_arrays(i) <= an_in_array;
    
    end generate;
    
    Is this a issue of VHDL can't handle this level of nesting or have I made an obvious silly mistake - any suggestions would be welcome. Fundamentally I'm trying to connect a parameterized number of modules together such that all connect to all except themselves.
     
    Last edited: Oct 19, 2010
    janeruth, Oct 19, 2010
    #1
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  2. janeruth

    janeruth

    Joined:
    Jul 23, 2009
    Messages:
    9
    For what it's worth in-case someone else has the same issue;

    The problem wasn't logic but rather my understanding of how generate works and although slightly complicated to explain with this example, is simple in the end;

    Generate was trying to make a new an_in_array each cycle of the outer loop but having problems as each new one created was then called the same thing with no distinction between them. It was basically overwriting the same array each cycle of the outer loop and hence creating the conflicts.

    The solution was to remove an_in_array as an intermediate completely and rather reference in arrays directly inside the inner loop as follows:

    Code:
        lable1:for i in 0 to PARAMETER generate
            begin
                    lable2:for j in 0 to PARAMETER generate
                        begin
                                    lable3: if (j>i) generate    
                                    begin
                                            in_arrays(i)(j-1) <= out_array(j);
                                    end generate;
    
                                    lable4: if (j<i) generate    
                                    begin
                                            in_arrays(i)(j) <= out_array(j);
                                    end generate;
                        end generate;
            end generate;
    
     
    janeruth, Oct 20, 2010
    #2
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