Generation of 4.096MHz clock from 7.680MHz clock

Discussion in 'VHDL' started by pankaj.goel, Nov 24, 2008.

  1. pankaj.goel

    pankaj.goel

    Joined:
    Nov 24, 2008
    Messages:
    8
    Likes Received:
    0
    Hi friends,
    In my design, I require an output clock 4.096MHz to be generated from 7.680MHz clock. I tried it but I am not getting acceptable output. Can anybody suggest something?

    regards
    pankaj
     
    Last edited: Nov 24, 2008
    pankaj.goel, Nov 24, 2008
    #1
    1. Advertisements

  2. pankaj.goel

    Ardni

    Joined:
    Jul 8, 2008
    Messages:
    23
    Likes Received:
    0
    Hi,
    What type of FPGA are you using?
    Have you thought about using a PLL to do this?
     
    Ardni, Nov 24, 2008
    #2
    1. Advertisements

  3. pankaj.goel

    jeppe

    Joined:
    Mar 10, 2008
    Messages:
    348
    Likes Received:
    0
    Location:
    Denmark
    Well - it will "cost you" 4 DCM's in a XiLinx FPGA to multiply the frequency with 8:

    With the new frequency 7.680 * 8 = 61.440 MHz can you get the wanted result by dividing with 15.
     
    jeppe, Nov 24, 2008
    #3
  4. pankaj.goel

    pankaj.goel

    Joined:
    Nov 24, 2008
    Messages:
    8
    Likes Received:
    0
    Hi Ardni...thanks for showing interest...

    I am using Altera cyclone II series FPGA for my design. The PLL doesn't support frequencies in the range of 4MHz and 7MHz. PLL works with 10MHz and above frequency. Try yourself.

    pankaj
     
    pankaj.goel, Nov 24, 2008
    #4
  5. pankaj.goel

    pankaj.goel

    Joined:
    Nov 24, 2008
    Messages:
    8
    Likes Received:
    0
    Hi Jeppe...thanks for the idea...I will try it using my altera cyclone II FPGA...

    pankaj
     
    pankaj.goel, Nov 24, 2008
    #5
  6. pankaj.goel

    Ardni

    Joined:
    Jul 8, 2008
    Messages:
    23
    Likes Received:
    0
    Hi,
    Thats a pity, as it can be implemented using an enhanced PLL on other families. I have done this on stratix devices without problems. But as you say the fast PLL type is only supported on Cyclone II.

    Anyway if I think of anything I´ll post it.
     
    Ardni, Nov 24, 2008
    #6
  7. pankaj.goel

    pankaj.goel

    Joined:
    Nov 24, 2008
    Messages:
    8
    Likes Received:
    0
    Hi jeppe...In my cyclone II device, I am unable to multiply 7.68MHz frequency. PLL is not accepting 7.68MHz as input. I think minimum value it accept is 10MHz.
    If you come across some solution, let me know.

    thanks
    pankaj
     
    pankaj.goel, Nov 25, 2008
    #7
    1. Advertisements

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Valentin Tihomirov

    Are clock and divided clock synchronous?

    Valentin Tihomirov, Oct 23, 2003, in forum: VHDL
    Replies:
    11
    Views:
    3,730
    louis lin
    Oct 28, 2003
  2. ALuPin

    Enabling clock generation

    ALuPin, Sep 30, 2004, in forum: VHDL
    Replies:
    1
    Views:
    703
    Nicolas Matringe
    Sep 30, 2004
  3. simon.stockton@baesystems.com
    Replies:
    4
    Views:
    952
    Peter Alfke
    Apr 27, 2006
  4. abhisheknag@gmail.com

    Arbitrary Clock Frequencies From Base Clock

    abhisheknag@gmail.com, Jun 19, 2006, in forum: VHDL
    Replies:
    5
    Views:
    2,654
    Ricardo
    Jun 23, 2006
  5. vu
    Replies:
    2
    Views:
    635
    Benjamin Todd
    Aug 27, 2006
  6. himassk
    Replies:
    1
    Views:
    1,394
    Paul Uiterlinden
    May 16, 2007
  7. J.Ram
    Replies:
    2
    Views:
    686
    perich
    Feb 6, 2009
  8. John W. Long

    HTML Generation (Next Generation CGI)

    John W. Long, Nov 22, 2003, in forum: Ruby
    Replies:
    4
    Views:
    661
    John W. Long
    Nov 24, 2003
Loading...