Generation of 4.096MHz clock from 7.680MHz clock

[pankaj.goel]

Hi friends,
In my design, I require an output clock 4.096MHz to be generated from 7.680MHz clock. I tried it but I am not getting acceptable output. Can anybody suggest something?

regards
pankaj

 

[Ardni]

Hi,
What type of FPGA are you using?
Have you thought about using a PLL to do this?

 

[jeppe]

Well - it will "cost you" 4 DCM's in a XiLinx FPGA to multiply the frequency with 8:

With the new frequency 7.680 * 8 = 61.440 MHz can you get the wanted result by dividing with 15.

 

[pankaj.goel]

Hi Ardni...thanks for showing interest...

I am using Altera cyclone II series FPGA for my design. The PLL doesn't support frequencies in the range of 4MHz and 7MHz. PLL works with 10MHz and above frequency. Try yourself.

pankaj

 

[pankaj.goel]

Hi Jeppe...thanks for the idea...I will try it using my altera cyclone II FPGA...

pankaj

 

[Ardni]

Hi,
Thats a pity, as it can be implemented using an enhanced PLL on other families. I have done this on stratix devices without problems. But as you say the fast PLL type is only supported on Cyclone II.

Anyway if I think of anything I´ll post it.

 

[pankaj.goel]

Hi jeppe...In my cyclone II device, I am unable to multiply 7.68MHz frequency. PLL is not accepting 7.68MHz as input. I think minimum value it accept is 10MHz.
If you come across some solution, let me know.

thanks
pankaj