Getting rid of packages in VHDL code

Discussion in 'VHDL' started by Nicholas Kinar, Dec 15, 2011.

  1. Hello,

    I am working with some VHDL code
    (http://www.xess.com/projects/sdramtst-1_6.zip), and I would like to use
    an automated tool to convert the VHDL code to Verilog
    (http://www.ocean-logic.com/downloads.htm).

    Unfortunately, the automated tool does not seem to support VHDL packages
    (containing functions). The "proper way" to convert the code would be
    to do the conversion by hand, but in the meantime:

    Is there a way to remove the packages from the VHDL code? Is there
    another way to bundle functions instead of using packages?

    There are two files in the download that demonstrate the use of
    packages: sdramcntl.vhd and common.vhd.

    Thank you,

    Nicholas
    Nicholas Kinar, Dec 15, 2011
    #1
    1. Advertising

  2. Icarus Verilog has been growing the ability to parse and elaborate
    VHDL, and it does support packages, although not yet functions. You
    can then use the verilog code generator to effectively get a
    conversion from VHDL to Verilog. The intent is to support mixed
    language VHDL/Verilog simulations, but the ability to translate
    comes more or less for free.

    All this is in the current git master, and it is very much a work
    in progress.

    On 12/14/2011 08:06 PM, Nicholas Kinar wrote:
    > Hello,
    >
    > I am working with some VHDL code
    > (http://www.xess.com/projects/sdramtst-1_6.zip), and I would like to use
    > an automated tool to convert the VHDL code to Verilog
    > (http://www.ocean-logic.com/downloads.htm).
    >
    > Unfortunately, the automated tool does not seem to support VHDL packages
    > (containing functions). The "proper way" to convert the code would be
    > to do the conversion by hand, but in the meantime:



    --
    Steve Williams "The woods are lovely, dark and deep.
    steve at icarus.com But I have promises to keep,
    http://www.icarus.com and lines to code before I sleep,
    http://www.picturel.com And lines to code before I sleep."
    Stephen Williams, Dec 15, 2011
    #2
    1. Advertising

  3. On 15/12/2011 12:03 PM, Stephen Williams wrote:
    >
    > Icarus Verilog has been growing the ability to parse and elaborate
    > VHDL, and it does support packages, although not yet functions. You
    > can then use the verilog code generator to effectively get a
    > conversion from VHDL to Verilog. The intent is to support mixed
    > language VHDL/Verilog simulations, but the ability to translate
    > comes more or less for free.
    >
    > All this is in the current git master, and it is very much a work
    > in progress.
    >


    That's great Stephen; you share some very marvelous news. So Icarus can
    indeed convert VHDL to Verilog!

    Icarus is actually the primary Verilog simulator that I use, and I
    didn't know this feature was making it into the git master. Over the
    past couple of days (and even weeks), I have been trying various
    proprietary simulators to do mixed-mode (VHDL and Verilog) simulation,
    but I find it very frustrating to work with these crippled and buggy
    software packages. I have been going around in circles trying to work
    with both VHDL and Verilog.

    I will clone the current Icarus git master and try to compile the most
    recent version of Icarus.

    1) Is there a tutorial/manual page on how to convert VHDL to Verilog
    using Icarus? I suspect that it could be similar to the one shown here:
    http://iverilog.wikia.com/wiki/Using_VHDL_Code_Generator

    2) Is there a way to get rid of the VHDL functions in the code by
    replacing the functions with a similar construct supported by Icarus
    Verilog?

    Many thanks,

    Nicholas
    Nicholas Kinar, Dec 15, 2011
    #3
  4. On 12/15/2011 10:59 AM, Nicholas Kinar wrote:
    > That's great Stephen; you share some very marvelous news. So Icarus can
    > indeed convert VHDL to Verilog!


    It can also simulate it without conversion. Or at least some bits
    of it. This is a work in progress.

    > Icarus is actually the primary Verilog simulator that I use, and I
    > didn't know this feature was making it into the git master. Over the
    > past couple of days (and even weeks), I have been trying various
    > proprietary simulators to do mixed-mode (VHDL and Verilog) simulation,
    > but I find it very frustrating to work with these crippled and buggy
    > software packages. I have been going around in circles trying to work
    > with both VHDL and Verilog.


    The main intent is to support mixed language simulations, not to make
    a converter. Conversion comes for free, but it sounds like you'd be
    just as happy with mixed language simulations.

    > 1) Is there a tutorial/manual page on how to convert VHDL to Verilog
    > using Icarus? I suspect that it could be similar to the one shown here:
    > http://iverilog.wikia.com/wiki/Using_VHDL_Code_Generator


    There is no tutorial or documentation on how to use the VHDL support.
    The page you point out above is for the VHDL code generator (i.e. to
    convert Verilog to VHDL) but you are trying to go the other way. It
    *is* very much a work in progress and documentation is needed.

    > 2) Is there a way to get rid of the VHDL functions in the code by
    > replacing the functions with a similar construct supported by Icarus
    > Verilog?


    Better would be to actually get Icarus Verilog to support the code
    that you have, rather then change it to what Icarus Verilog can support,
    but in the short term it may be more expedient to change your code to
    what Icarus Verilog can support. No, I do not know of any tools that
    can do that automatically.

    You might want to lurk and/or ask about it on the iverilog-devel
    mailing list.


    P.S. (and pardon the marketing) The VHDL/mixed language support was
    sponsored/paid for. That model works well for me and if there are
    specific needs you would like addressed with higher priority, I, and
    possibly others on the iverilog-devel mailing list, am open to doing
    contract work to address your specific needs. I am actively looking
    for more sponsorships for this open source work.

    --
    Steve Williams "The woods are lovely, dark and deep.
    steve at icarus.com But I have promises to keep,
    http://www.icarus.com and lines to code before I sleep,
    http://www.picturel.com And lines to code before I sleep."
    Stephen Williams, Dec 15, 2011
    #4
  5. On 15/12/2011 1:20 PM, Stephen Williams wrote:
    > The main intent is to support mixed language simulations, not to make
    > a converter. Conversion comes for free, but it sounds like you'd be
    > just as happy with mixed language simulations.


    Thanks for your response, Stephen! I would indeed be just as happy with
    mixed language simulations.

    >
    >> 1) Is there a tutorial/manual page on how to convert VHDL to Verilog
    >> using Icarus? I suspect that it could be similar to the one shown here:
    >> http://iverilog.wikia.com/wiki/Using_VHDL_Code_Generator

    >
    > There is no tutorial or documentation on how to use the VHDL support.
    > The page you point out above is for the VHDL code generator (i.e. to
    > convert Verilog to VHDL) but you are trying to go the other way. It
    > *is* very much a work in progress and documentation is needed.


    Okay, I suppose that there has to be some command-line switches that can
    be used to do the conversion. I suspect that either reading the code or
    looking at the command-line help would be insightful. I will try to ask
    about it on the iverilog-devel mailing list.

    >
    >> 2) Is there a way to get rid of the VHDL functions in the code by
    >> replacing the functions with a similar construct supported by Icarus
    >> Verilog?

    >
    > Better would be to actually get Icarus Verilog to support the code
    > that you have, rather then change it to what Icarus Verilog can support,
    > but in the short term it may be more expedient to change your code to
    > what Icarus Verilog can support. No, I do not know of any tools that
    > can do that automatically.
    >
    > You might want to lurk and/or ask about it on the iverilog-devel
    > mailing list.


    Hmm, I would wonder if I could simply modify the VHDL file by hand to
    use something similar to functions. I will try to compile the Icarus
    Verilog code from git and then ask about changing the code on the
    iverilog-devel mailing list.

    Nicholas
    Nicholas Kinar, Dec 15, 2011
    #5
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. Paul  Smith
    Replies:
    0
    Views:
    720
    Paul Smith
    Nov 18, 2003
  2. afd
    Replies:
    1
    Views:
    8,273
    Colin Paul Gloster
    Mar 23, 2007
  3. Amal
    Replies:
    1
    Views:
    1,740
    vipinlal
    Mar 4, 2010
  4. David Lyon
    Replies:
    19
    Views:
    557
    David Lyon
    Apr 24, 2009
  5. Ian
    Replies:
    3
    Views:
    159
Loading...

Share This Page