Glitches in post-layout (PAR) simulation

Discussion in 'VHDL' started by Manny, Oct 12, 2006.

  1. Manny

    Manny Guest

    Hey all,

    I've managed to synthesize a particular DSP core on Actel's fusion
    FPGA. I'm using this as a benchmark to assess their suitability for
    further integration. I'm a bit new when it comes to Actel. Anyway, it
    seems that when running post-PAR simulation I end up having a periodic
    pattern of 1ns wide glitches in my output signal every like 4 or
    slightly less sampling periods. My design is fully synchronous. I have
    no clue whatsoever about the source of the glitches. I even tried to
    leave some temporal margin before doing the final output assignment
    (for thigs to settle down) but it didn't work. Would really appreciate
    it if anybody can give me an insight on possible problematic sources.
    I'm yet to run my design in hardware as I'm still waiting for the kit
    to arrive.

    Thanks in advance guys.

    Cheers,
    Manny, Oct 12, 2006
    #1
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  2. Manny

    Zara Guest

    On 12 Oct 2006 11:55:43 -0700, "Manny" <> wrote:

    >Hey all,
    >
    >I've managed to synthesize a particular DSP core on Actel's fusion
    >FPGA. I'm using this as a benchmark to assess their suitability for
    >further integration. I'm a bit new when it comes to Actel. Anyway, it
    >seems that when running post-PAR simulation I end up having a periodic
    >pattern of 1ns wide glitches in my output signal every like 4 or
    >slightly less sampling periods. My design is fully synchronous. I have
    >no clue whatsoever about the source of the glitches. I even tried to
    >leave some temporal margin before doing the final output assignment
    >(for thigs to settle down) but it didn't work. Would really appreciate
    >it if anybody can give me an insight on possible problematic sources.
    >I'm yet to run my design in hardware as I'm still waiting for the kit
    >to arrive.
    >
    >Thanks in advance guys.
    >
    >Cheers,



    Typically, any synchronous system consist of some asynchronous logic
    connected to the input of some synchronous registers, whose ouputs
    generate the "result" signals via some asynchronous logic.

    You should look at that last part, or at a"outpuit" logic that
    combines directly some input signals (optionally plus some synchronous
    signals).

    For instance, you may have an FSM whihch takes some inputs, and
    changes state following this inputs and some feedback.

    The statements of the like:

    my_output <= async_input when FSM=STATE1 else '0';

    are possible sources of glitches

    regrads,

    Zara
    Zara, Oct 13, 2006
    #2
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