got crazy about variable index...

Discussion in 'VHDL' started by cracker007, Nov 8, 2009.

  1. cracker007

    cracker007

    Joined:
    Nov 8, 2009
    Messages:
    1
    Hi, I am struggling with a weired thing:

    type Reg is array(0 to 3) of std_logic_vector(7 downto 0);
    ...
    Rd : in STD_LOGIC_VECTOR (1 downto 0); --this is in ports declaration

    function decode(R_code : in std_logic_vector(1 downto 0))
    return integer is
    variable tmp : integer;
    begin
    case R_code is
    when "00" => tmp:=0;
    when "01" => tmp:=1;
    when "10" => tmp:=2;
    when "11" => tmp:=3;
    when others => NULL;
    end case;
    return tmp;
    end;

    process (CLK)
    variable R : Reg;
    variable tmp: integer;
    begin
    ...
    tmp :=decode(Rd);
    R_load(R(tmp)(2 downto 0),Rs);
    ...

    The R_load function is not important.
    The weired thing is that the last function doesn't work as it should be. But the following one works well:

    tmp :=2;
    R_load(R(tmp)(2 downto 0),Rs);

    Does it mean a big difference to VHDL? (By the way, I am quite sure that the decode(Rd) function has no problem cause I tested it a lot of times).

    As you see, I just want to make the first index of R depending on Rd.
    What can I do now?
     
    cracker007, Nov 8, 2009
    #1
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