HELP!a bug in testbench

Discussion in 'VHDL' started by laSiA, Jun 3, 2009.

  1. laSiA

    laSiA

    Joined:
    Jun 3, 2009
    Messages:
    2
    I'm writing a testbench.There are several bugs i dont understand.

    The compiler shows as following:
    No feasible entries for subprogram "conv_integer".
    Bad expression in left operand of infix expression "-".
    Bad right hand side (infix expression) in variable assignment.

    And they all commence on the red line.Thanks!:veryprou:

    -- Provide message block and check the result
    sti_datain: PROCESS
    VARIABLE tmp_din: STD_LOGIC_VECTOR(63 DOWNTO 0);
    VARIABLE tmp_dout: STD_LOGIC_VECTOR(63 DOWNTO 0);
    VARIABLE tmp_len: STD_LOGIC_VECTOR(63 DOWNTO 0);
    VARIABLE len_cout: INTEGER;

    FILE vector_file: text IS IN "Short.txt";
    VARIABLE l: LINE; --define the line buffer
    VARIABLE good, good_val: BOOLEAN; --status of read operation

    BEGIN

    -- skip four-line commencement
    READLINE(vector_file, l);
    READLINE(vector_file, l);
    READLINE(vector_file, l);
    READLINE(vector_file, l);

    WHILE NOT ENDFILE(vector_file) Loop

    WAIT UNTIL len_vld='1';
    READLINE(vector_file, l);
    HREAD(l,tmp_len,good);
    ASSERT good
    report"Bad message length value";
    data_in<=tmp_len;
    len_cout := conv_integer(tmp_len)/64-1;

    --skip one line to read Msg
    READLINE(vector_file, l);

    L1:for i in 0 downto len_cout LOOP
    READLINE(vector_file, l);
    HREAD(l, tmp_din, good);
    ASSERT good REPORT "Bad message message block value";
    data_in<=tmp_din;
    wait for MsgPeriod;
    end loop L1;

    --skip one line to read digest_out
    READLINE(vector_file, l);

    WAIT UNTIL digest_out_vld='1';

    READLINE(vector_file, l);
    HREAD(l, tmp_dout, good_val);
    ASSERT good_val REPORT "Bad digest vector value 1";
    ASSERT (tmp_dout=digest_out) REPORT "Output mismatch 1";
    WAIT FOR DgtPeriod;
    READLINE(vector_file, l);
    HREAD(l, tmp_dout, good_val);
    ASSERT good_val REPORT "Bad digest vector value 2";
    ASSERT (tmp_dout=digest_out) REPORT "Output mismatch 2";
    WAIT FOR DgtPeriod;
    READLINE(vector_file, l);
    HREAD(l, tmp_dout, good_val);
    ASSERT good_val REPORT "Bad digest vector value 3";
    ASSERT (tmp_dout=digest_out) REPORT "Output mismatch 3";
    WAIT FOR DgtPeriod;
    READLINE(vector_file, l);
    HREAD(l, tmp_dout, good_val);
    ASSERT good_val REPORT "Bad digest vector value 4";
    ASSERT (tmp_dout=digest_out) REPORT "Output mismatch 4";

    END Loop;

    WAIT;

    END PROCESS;
     
    laSiA, Jun 3, 2009
    #1
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  2. laSiA

    JohnDuq

    Joined:
    Dec 9, 2008
    Messages:
    88
    conv_Integer is defined in the Std_Logic_Arith library.

    use ieee.std_logic_arith.all

    Check out this link for some good tips:

    www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf


    Once the compiler doesn't know what to do with that function it gets confused on the rest of the line too.
     
    JohnDuq, Jun 4, 2009
    #2
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  3. laSiA

    laSiA

    Joined:
    Jun 3, 2009
    Messages:
    2
    I declare that library in the beginning.So,that's not the problem.Any other suggestion?
     
    laSiA, Jun 5, 2009
    #3
  4. laSiA

    JohnDuq

    Joined:
    Dec 9, 2008
    Messages:
    88
    From http://www.cs.sfu.ca/~ggbaker/reference/std_logic/arith/conv_integer.html

    The conv_integer function
    function conv_integer(arg: integer) return integer;
    function conv_integer(arg: unsigned) return integer;
    function conv_integer(arg: signed) return integer;
    function conv_integer(arg: std_ulogic) return small_int;

    These functions convert the arg argument to an integer. If the argument contains any undefined elements, a runtime warning is produced and 0 is returned.

    The function provided by the std_logic_arith library can't convert a std_logic_vector to an integer because it is impossible to determine if it represents an unsigned or signed value. Functions that do this are included in the std_logic_unsigned and std_logic_signed libraries.
     
    JohnDuq, Jun 5, 2009
    #4
  5. laSiA

    JohnDuq

    Joined:
    Dec 9, 2008
    Messages:
    88
    www dot cs dot sfu dot ca/~ggbaker/reference/std_logic/arith/conv_integer.html

    The conv_integer function
    function conv_integer(arg: integer) return integer;
    function conv_integer(arg: unsigned) return integer;
    function conv_integer(arg: signed) return integer;
    function conv_integer(arg: std_ulogic) return small_int;

    These functions convert the arg argument to an integer. If the argument contains any undefined elements, a runtime warning is produced and 0 is returned.

    The function provided by the std_logic_arith library can't convert a std_logic_vector to an integer because it is impossible to determine if it represents an unsigned or signed value. Functions that do this are included in the std_logic_unsigned and std_logic_signed libraries.
     
    JohnDuq, Jun 5, 2009
    #5
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