Help in SRAM block??

Discussion in 'VHDL' started by dcreddy1980, Dec 20, 2004.

  1. dcreddy1980

    dcreddy1980 Guest

    I dont know where i went wrong in the following code,when i simulate the
    code...i am getting RWD <= "UUUUUU"in the waveform results....

    entity SRAM is
    port(CADDR : in std_logic_vector(3 downto 0);
    RADDR : in std_logic_vector(6 downto 0);
    RWD : inout std_logic_vector(15 downto 0);
    BNKSEL : in std_logic;
    RDCAS : in std_logic;
    WRCAS : in std_logic;
    DTRDY : out std_logic);
    end SRAM;

    architecture behaviour of SRAM is
    begin
    process(BNKSEL,RDCAS,WRCAS,CADDR,RADDR,RWD)
    subtype tmp is std_logic_vector(15 downto 0);
    type memory_array is array(integer range 0 to 127,integer range 0 to
    15);---128 rows and 16 columns
    variable mem : memory_array;
    begin
    if(BNKSEL'event and BNKSEL = '1') then
    if(RDCAS = '1') then
    RWD <=
    mem(conv_integer(unsigned(CADDR)),conv_integer(unsigned(RADDR)));
    DTRDY <= '1';
    end if;
    if(WRCAS = '1') then
    mem(conv_integer(unsigned(CADDR)),conv_integer(unsigned(RADDR))) :=
    RWD;
    DTRDY <= '0';
    end if;
    end if;
    end process;
    end behaviour;


    TESTBENCH :
    ------------

    entity tb_SRAM is
    end tb_SRAM;

    architecture tb of tb_SRAM is
    component SRAM
    port(CADDR : in std_logic_vector(3 downto 0);
    RADDR : in std_logic_vector(6 downto 0);
    RWD : inout std_logic_vector(15 downto 0);
    BNKSEL : in std_logic;
    RDCAS : in std_logic;
    WRCAS : in std_logic;
    DTRDY : out std_logic);
    end component;
    signal RDCAS,WRCAS,DTRDY,BNKSEL : std_logic;
    signal CADDR : std_logic_vector(6 downto 0);
    signal RADDR : std_logic_vector(3 downto 0);
    signal RWD : std_logic_vector(15 downto 0);
    begin

    UUT : SRAM port map(CADDR,RADDR,RWD,BNKSEL,RDCAS,WRCAS,DTRDY);

    CADDR <= "0010010";
    RADDR <= "0010";
    RWD <= "0001000100010001";
    BNKSEL <= '0','1' after 8 ns,'0' after 16 ns,'1' after 24 ns,'0' after 30
    ns;
    RDCAS <= '0','1' after 26 ns,'0' after 34 ns;
    WRCAS <= '0','1' after 10 ns,'0' after 18 ns;

    end tb;


    is there any correction in my testbench???if so,can u plz rectify my
    mistake....


    Regards,
    dcreddy1980
     
    dcreddy1980, Dec 20, 2004
    #1
    1. Advertising

  2. dcreddy1980 wrote:
    > I dont know where i went wrong in the following code,when i simulate the
    > code...i am getting RWD <= "UUUUUU"in the waveform results....


    I would expect it to be XXXX.

    > UUT : SRAM port map(CADDR,RADDR,RWD,BNKSEL,RDCAS,WRCAS,DTRDY);
    >
    > CADDR <= "0010010";
    > RADDR <= "0010";
    > RWD <= "0001000100010001";
    > BNKSEL <= '0','1' after 8 ns,'0' after 16 ns,'1' after 24 ns,'0' after 30
    > ns;
    > RDCAS <= '0','1' after 26 ns,'0' after 34 ns;
    > WRCAS <= '0','1' after 10 ns,'0' after 18 ns;
    >
    > end tb;
    >
    > is there any correction in my testbench???if so,can u plz rectify my
    > mistake....


    RWD is an inout, so in the testbench if you want to read a value from
    the RAM, you should set RWD hi-Z: RWD <= (OTHERS => 'Z');

    The same goes for your RAM: it should drive RWD hi-Z if it is not being
    read.

    Paul.
     
    Paul Uiterlinden, Dec 21, 2004
    #2
    1. Advertising

Want to reply to this thread or ask your own question?

It takes just 2 minutes to sign up (and it's free!). Just click the sign up button to choose a username and then you can ask your own questions on the forum.
Similar Threads
  1. sarah
    Replies:
    1
    Views:
    1,675
    Jan Panteltje
    Aug 13, 2003
  2. Michael

    SRAM vs Cache

    Michael, Sep 18, 2003, in forum: VHDL
    Replies:
    4
    Views:
    6,390
    Mario Trams
    Sep 22, 2003
  3. moe
    Replies:
    3
    Views:
    839
    Jim Wu
    Nov 16, 2003
  4. KM
    Replies:
    1
    Views:
    2,173
    Mike Treseler
    Dec 5, 2003
  5. morrell
    Replies:
    1
    Views:
    1,006
    roy axenov
    Oct 10, 2006
Loading...

Share This Page