How do I constraint multiple clock cycle in Altera?

Discussion in 'VHDL' started by news reader, May 19, 2007.

  1. news reader

    news reader Guest

    Hello everybody,

    My Altera design uses multiple clock cycle and negative clock edge, how do I
    constraint it?
    Here is my code, absolute_addr is generated 1.5 clocks earlier before
    consumption.

    I am reading the Quartus II Classic timing analyzer manual, but am not clear
    how to constrain
    this logic.

    Hope you can help me out.

    Many thanks from newsreader.




    // My code segment

    reg start_sequence;
    reg [2:0] addr_en; // one-hot
    reg [31:0] absolute_addr;
    reg [1:0] ram_ba;
    reg [15:0] ram_row;
    reg [7:0] ram_col;

    always @(posedge clk_100m or negedge arst_n) begin
    if (!arst_n) begin
    addr_en <= 2'd0;
    end
    else begin
    addr_en <= {addr_en[1:0], start_sequence};
    end
    end

    always @(posedge clk_100m or negedge arst_n) begin
    if (!arst_n) begin
    absolute_addr <= 26'd0;
    end
    else begin
    if (addr_en[0])
    absolute_addr <= complex_addr_gen_func(......); // Expecting take 12ns
    end
    end

    always @(negedge clk_100m or negedge arst_n) begin
    if (!arst_n) begin
    ram_ba <= 2'd0;
    ram_row <= 16'd0;
    ram_col <= 8'd0;
    end
    else begin
    if (addr_en[2]) begin
    ram_ba <= absolute_addr[25:24];
    ram_row <= absolute_addr[23:8];
    ram_col <= absolute_addr[7:0];
    end
    else begin
    ram_ba <= 2'd0;
    ram_row <= 16'd0;
    ram_col <= 8'd0;
    end
    end
    end
    news reader, May 19, 2007
    #1
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  2. Hi!
    Create a separate negative clock signal, either as a primary port (do
    the inversion outside this module)
    and constraint this module by creating 2 clocks, phase shifted by 180,
    and adding a multicycle path between these 2 clocks
    Let me know if it helps

    Rajkumar...

    news reader wrote:
    > Hello everybody,
    >
    > My Altera design uses multiple clock cycle and negative clock edge, how do I
    > constraint it?
    > Here is my code, absolute_addr is generated 1.5 clocks earlier before
    > consumption.
    >
    > I am reading the Quartus II Classic timing analyzer manual, but am not clear
    > how to constrain
    > this logic.
    >
    > Hope you can help me out.
    >
    > Many thanks from newsreader.
    >
    >
    >
    >
    > // My code segment
    >
    > reg start_sequence;
    > reg [2:0] addr_en; // one-hot
    > reg [31:0] absolute_addr;
    > reg [1:0] ram_ba;
    > reg [15:0] ram_row;
    > reg [7:0] ram_col;
    >
    > always @(posedge clk_100m or negedge arst_n) begin
    > if (!arst_n) begin
    > addr_en <= 2'd0;
    > end
    > else begin
    > addr_en <= {addr_en[1:0], start_sequence};
    > end
    > end
    >
    > always @(posedge clk_100m or negedge arst_n) begin
    > if (!arst_n) begin
    > absolute_addr <= 26'd0;
    > end
    > else begin
    > if (addr_en[0])
    > absolute_addr <= complex_addr_gen_func(......); // Expecting take 12ns
    > end
    > end
    >
    > always @(negedge clk_100m or negedge arst_n) begin
    > if (!arst_n) begin
    > ram_ba <= 2'd0;
    > ram_row <= 16'd0;
    > ram_col <= 8'd0;
    > end
    > else begin
    > if (addr_en[2]) begin
    > ram_ba <= absolute_addr[25:24];
    > ram_row <= absolute_addr[23:8];
    > ram_col <= absolute_addr[7:0];
    > end
    > else begin
    > ram_ba <= 2'd0;
    > ram_row <= 16'd0;
    > ram_col <= 8'd0;
    > end
    > end
    > end
    Rajkumar Kadam, May 19, 2007
    #2
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